參數(shù)資料
型號： ENC424J600T-I/PT
廠商： Microchip Technology
文件頁數(shù)： 12/168頁
文件大小： 0K
描述： IC ETHERNET CTRLR W/SPI 44-TQFP
視頻文件： Fast 100 Mbps Ethernet PICtail Plus Overview
標(biāo)準(zhǔn)包裝： 1,200
控制器類型： 以太網(wǎng)控制器（IEEE 802.3）
接口： SPI
電源電壓： 3 V ~ 3.6 V
電流 - 電源： 96mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-TQFP
供應(yīng)商設(shè)備封裝： 44-TQFP（10x10）
包裝： 帶卷 (TR)
配用： AC164132-ND - BOARD DAUGHTER PICTAIL ETHERNET
2007 Microchip Technology Inc.
DS39599G-page 107
PIC18F2220/2320/4220/4320
10.3
PORTC, TRISC and LATC
Registers
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register read and write the latched output value for
PORTC.
PORTC is multiplexed with several peripheral functions
(Table 10-5). The pins have Schmitt Trigger input buff-
ers. RC1 is normally configured by Configuration bit,
CCP2MX (CONFIG3H<0>), as the default peripheral
pin of the CCP2 module (default/erased state,
CCP2MX = 1).
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents even though a peripheral device
may be overriding one or more of the pins.
EXAMPLE 10-3:
INITIALIZING PORTC
FIGURE 10-10:
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
Note:
On a Power-on Reset, these pins are
configured as digital inputs.
CLRF
PORTC
; Initialize PORTC by
; clearing output
; data latches
CLRF
LATC
; Alternate method
; to clear output
; data latches
MOVLW
0xCF
; Value used to
; initialize data
; direction
MOVWF
TRISC
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
Data Bus
WR LATC or
WR TRISC
RD TRISC
Peripheral Data Out
0
1
RD PORTC
Peripheral Data In
WR PORTC
RD LATC
Peripheral Output
Schmitt
Port/Peripheral Select(2)
Enable(3)
P
N
VSS
VDD
I/O pin(1)
Note 1:
I/O pins have diode protection to VDD and VSS.
2:
Port/Peripheral Select signal selects between port data (output) and peripheral output.
3:
Peripheral Output Enable is only active if Peripheral Select is active.
Data Latch
TRIS Latch
Trigger
Q
D
Q
CK
Q
D
Q
CK
Q
D
EN
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