參數(shù)資料
型號(hào)： ENC424J600T-I/PT
廠商： Microchip Technology
文件頁數(shù)： 94/168頁
文件大?。?/td> 0K
描述： IC ETHERNET CTRLR W/SPI 44-TQFP
視頻文件： Fast 100 Mbps Ethernet PICtail Plus Overview
標(biāo)準(zhǔn)包裝： 1,200
控制器類型： 以太網(wǎng)控制器（IEEE 802.3）
接口： SPI
電源電壓： 3 V ~ 3.6 V
電流 - 電源： 96mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-TQFP
供應(yīng)商設(shè)備封裝： 44-TQFP（10x10）
包裝： 帶卷 (TR)
配用： AC164132-ND - BOARD DAUGHTER PICTAIL ETHERNET
2007 Microchip Technology Inc.
DS21993C-page 29
PIC16CR7X
3.0
READING PROGRAM MEMORY
The ROM Program Memory is readable during normal
operation over the entire VDD range. It is indirectly
addressed through Special Function Registers (SFR).
Up to 14-bit numbers can be stored in memory for use
as calibration parameters, serial numbers, packed 7-bit
ASCII, etc. Executing a program memory location
containing data that forms an invalid instruction results
in a NOP.
There are five SFRs used to read the program and
memory. These registers are:
PMCON1
PMDATA
PMDATH
PMADR
PMADRH
The program memory allows word reads. Program
memory access allows for checksum calculation and
reading calibration tables.
When interfacing to the program memory block, the
PMDATH:PMDATA registers form a two-byte word,
which
holds
the
14-bit
data
for
reads.
The
PMADRH:PMADR registers form a two-byte word,
which holds the 13-bit address of the ROM location
being accessed. These devices can have up to 8K
words of program ROM, with an address range from 0h
to 3FFFh. The unused upper bits in both the PMDATH
and PMADRH registers are not implemented and read
as ‘0’s.
3.1
PMADR
The address registers can address up to a maximum of
8K words of program ROM.
When selecting a program address value, the MSB of
the address is written to the PMADRH register and the
LSB is written to the PMADR register. The upper MSb’s
of PMADRH must always be clear.
3.2
PMCON1 Register
PMCON1 is the control register for memory accesses.
The control bit RD initiates read operations. This bit
cannot be cleared, only set, in software. It is cleared in
hardware at the completion of the read operation.
REGISTER 3-1:
PMCON1: (ADDRESS 18Ch)
R-1
U-0
U-x
U-0
R/S-0
reserved
—
—RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Reserved: Read as ‘1’
bit 6-1
Unimplemented: Read as ‘0’
bit 0
RD: Read Control bit
1
= Initiates a ROM read, RD is cleared in hardware. The RD bit can only be set (not cleared) in
software.
0
= ROM read completed
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