參數(shù)資料
型號(hào)： EP2AGX65DF25C5N
廠商： Altera
文件頁(yè)數(shù)： 70/90頁(yè)
文件大?。?/td> 0K
描述： IC ARRIA II GX FPGA 65K 572FBGA
產(chǎn)品培訓(xùn)模塊： Arria II GX FPGA
Three Reasons to Use FPGA's in Industrial Designs
特色產(chǎn)品： Arria? II GX FPGAs
標(biāo)準(zhǔn)包裝： 5
系列： Arria II GX
LAB/CLB數(shù)： 2530
邏輯元件/單元數(shù)： 60214
RAM 位總計(jì)： 5371904
輸入/輸出數(shù)： 252
電源電壓： 0.87 V ~ 0.93 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 572-FBGA
供應(yīng)商設(shè)備封裝： 572-FBGA
其它名稱： 544-2641
1–64
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
December 2013
Altera Corporation
Table 1–54 lists the high-speed I/O timing for Arria II GZ devices.
fHSDR (data rate)
SERDES factor
J = 3 to 10
945
945
740
640
Mbps
SERDES factor
J = 2 (using
DDR registers)
Mbps
SERDES factor
J = 1 (using
SDR registers)
Mbps
Soft-CDR PPM
tolerance
Soft-CDR
mode
—
300
—
300
—
300
—
300
PPM
DPA run length
DPA mode
—
10,000
—
10,000
—
10,000
—
10,000
UI
Sampling
window (SW)
Non-DPA mode
—
300
—
300
—
350
—
400
ps
Notes to Table 1–53:
(1) fHSCLK_IN = fHSDR / W. Use W to determine the supported selection of input reference clock frequencies for the desired data rate.
(2) Applicable for interfacing with DPA receivers only. For interfacing with non-DPA receivers, you must calculate the leftover timing margin in the
receiver by performing link timing closure analysis. For Arria II GX transmitter to Arria II GX non-DPA receiver, the maximum supported data
rate is 945 Mbps. For data rates above 840 Mbps, perform PCB trace compensation by adjusting the PCB trace length for LVDS channels to
improve channel-to-channel skews.
(3) The minimum and maximum specification depends on the clock source (for example, PLL and clock pin) and the clock routing resource you
use (global, regional, or local). The I/O differential buffer and input register do not have a minimum toggle rate.
(4) The specification is only applicable under the influence of core noise.
(5) Applicable for true LVDS using dedicated SERDES only.
(6) Dedicated SERDES and DPA features are only available on the right banks.
(7) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew
margin, transmitter channel-to-channel skew, and the receiver sampling margin to determine the leftover timing margin.
Table 1–53. High-Speed I/O Specifications for Arria II GX Devices (Part 4 of 4)
Symbol
Conditions
I3
C4
C5,I5
C6
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Table 1–54. High-Speed I/O Specifications for Arria II GZ Devices (Note 1), (2), (10) (Part 1 of 3)
Symbol
Conditions
C3, I3
C4, I4
Unit
Min
Typ
Max
Min
Typ
Max
Clock
fHSCLK_in (input clock
frequency) true
differential I/O
standards
Clock boost factor
W = 1 to 40 (3)
5
—
717
5
—
717
MHz
fHSCLK_in (input clock
frequency) single
ended I/O standards
Clock boost factor
W = 1 to 40 (3)
5
—
717
5
—
717
MHz
fHSCLK_in (input clock
frequency) single
ended I/O standards
Clock boost factor
W = 1 to 40 (3)
5
—
420
5
—
420
MHz
相關(guān)PDF資料
PDF描述
VE-24W-CY-S CONVERTER MOD DC/DC 5.5V 50W
TAJC685K035H CAP TANT 6.8UF 35V 10% 2312
EP1AGX50DF780C6N IC ARRIA GX FPGA 50K 780FBGA
TACL105K010R CAP TANT 1UF 10V 10% 0603
EP1AGX50DF1152C6N IC ARRIA GX FPGA 50K 1152FBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP2AGX65DF25C6 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Arria II GX 2530 LABs 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX65DF25C6ES 制造商:Altera Corporation 功能描述:FPGA Arria
EP2AGX65DF25C6N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Arria II GX 2530 LABs 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX65DF25C6NES 制造商:Altera Corporation 功能描述:FPGA Arria 制造商:Altera Corporation 功能描述:FPGA Arria? II GX Family 60214 Cells 400MHz 40nm Technology 0.9V 572-Pin FC-FBGA 制造商:Altera Corporation 功能描述:IC ARRIA II GX FPGA 572FBGA
EP2AGX65DF25I3 功能描述:IC ARRIA II GX FPGA 65K 572FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Arria II GX 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*