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參數(shù)資料
| 型號： | EPF10K100ARI240-3N |
| 廠商： | Altera |
| 文件頁數(shù)： | 2/128頁 |
| 文件大小： | 0K |
| 描述： | IC FLEX 10KA FPGA 100K 240-RQFP |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 產(chǎn)品變化通告： | Package Change 30/Jun/2010 |
| 標(biāo)準包裝： | 24 |
| 系列： | FLEX-10K® |
| LAB/CLB數(shù)： | 624 |
| 邏輯元件/單元數(shù)： | 4992 |
| RAM 位總計： | 24576 |
| 輸入/輸出數(shù)： | 189 |
| 門數(shù)： | 158000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 240-BFQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 240-RQFP（32x32） |
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10
Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Logic functions are implemented by programming the EAB with a read-
only pattern during configuration, creating a large LUT. With LUTs,
combinatorial functions are implemented by looking up the results, rather
than by computing them. This implementation of combinatorial functions
can be faster than using algorithms implemented in general logic, a
performance advantage that is further enhanced by the fast access times
of EABs. The large capacity of EABs enables designers to implement
complex functions in one logic level without the routing delays associated
with linked LEs or field-programmable gate array (FPGA) RAM blocks.
For example, a single EAB can implement a 4
× 4 multiplier with eight
inputs and eight outputs. Parameterized functions such as LPM functions
can automatically take advantage of the EAB.
The EAB provides advantages over FPGAs, which implement on-board
RAM as arrays of small, distributed RAM blocks. These FPGA RAM
blocks contain delays that are less predictable as the size of the RAM
increases. In addition, FPGA RAM blocks are prone to routing problems
because small blocks of RAM must be connected together to make larger
blocks. In contrast, EABs can be used to implement large, dedicated blocks
of RAM that eliminate these timing and routing concerns.
EABs can be used to implement synchronous RAM, which is easier to use
than asynchronous RAM. A circuit using asynchronous RAM must
generate the RAM write enable (WE) signal, while ensuring that its data
and address signals meet setup and hold time specifications relative to the
WE
signal. In contrast, the EAB’s synchronous RAM generates its own WE
signal and is self-timed with respect to the global clock. A circuit using the
EAB’s self-timed RAM need only meet the setup and hold time
specifications of the global clock.
When used as RAM, each EAB can be configured in any of the following
sizes: 256
× 8, 512 × 4, 1,024 × 2, or 2,048 × 1. See Figure 2.
Figure 2. EAB Memory Configurations
256
× 8
512
× 4
1,024
× 2
2,048
× 1
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