參數(shù)資料
型號: EPF10K100ARI240-3N
廠商: Altera
文件頁數(shù): 88/128頁
文件大?。?/td> 0K
描述: IC FLEX 10KA FPGA 100K 240-RQFP
產(chǎn)品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
產(chǎn)品變化通告: Package Change 30/Jun/2010
標準包裝: 24
系列: FLEX-10K®
LAB/CLB數(shù): 624
邏輯元件/單元數(shù): 4992
RAM 位總計: 24576
輸入/輸出數(shù): 189
門數(shù): 158000
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 240-BFQFP 裸露焊盤
供應商設備封裝: 240-RQFP(32x32)
62
Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Table 35. EAB Timing Macroparameters
Symbol
Parameter
Conditions
tEABAA
EAB address access delay
tEABRCCOMB
EAB asynchronous read cycle time
tEABRCREG
EAB synchronous read cycle time
tEABWP
EAB write pulse width
tEABWCCOMB
EAB asynchronous write cycle time
tEABWCREG
EAB synchronous write cycle time
tEABDD
EAB data-in to data-out valid delay
tEABDATACO
EAB clock-to-output delay when using output registers
tEABDATASU
EAB data/address setup time before clock when using input register
tEABDATAH
EAB data/address hold time after clock when using input register
tEABWESU
EAB WE setup time before clock when using input register
tEABWEH
EAB WE hold time after clock when using input register
tEABWDSU
EAB data setup time before falling edge of write pulse when not using input
registers
tEABWDH
EAB data hold time after falling edge of write pulse when not using input
registers
tEABWASU
EAB address setup time before rising edge of write pulse when not using
input registers
tEABWAH
EAB address hold time after falling edge of write pulse when not using input
registers
tEABWO
EAB write enable to data output valid delay
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