參數(shù)資料
型號(hào)： EPM2210F256A4N
廠商： ALTERA CORP
元件分類： PLD
英文描述： FLASH PLD, PBGA256
封裝： 17 X 17 MM, 1 MM PITCH, LEAD FREE, FBGA-256
文件頁數(shù)： 50/108頁
文件大小： 1342K
代理商： EPM2210F256A4N
2–38Core Version a.b.c variable
Altera Corporation
MAX II Device Handbook, Volume 1
March 2008
I/O Structure
Slew-Rate Control
The output buffer for each MAX II device I/O pin has a programmable
output slew-rate control that can be configured for low noise or
high-speed performance. A faster slew rate provides high-speed
transitions for high-performance systems. However, these fast transitions
may introduce noise transients into the system. A slow slew rate reduces
system noise, but adds a nominal output delay to rising and falling edges.
The lower the voltage standard (for example, 1.8-V LVTTL) the larger the
output delay when slow slew is enabled. Each I/O pin has an individual
slew-rate control, allowing the designer to specify the slew rate on a
pin-by-pin basis. The slew-rate control affects both the rising and falling
edges.
Open-Drain Output
MAX II devices provide an optional open-drain (equivalent to
open-collector) output for each I/O pin. This open-drain output enables
the device to provide system-level control signals (for example, interrupt
and write enable signals) that can be asserted by any of several devices.
This output can also provide an additional wired-OR plane.
Programmable Ground Pins
Each unused I/O pin on MAX II devices can be used as an additional
ground pin. This programmable ground feature does not require the use
of the associated LEs in the device. In the Quartus II software, unused
pins can be set as programmable GND on a global default basis or they
can be individually assigned. Unused pins also have the option of being
set as tri-stated input pins.
1.5-V LVCMOS
4
2
Note to Table 2–6:
(1)
The IOH current strength numbers shown are for a condition of a VOUT = VOH
minimum, where the VOH minimum is specified by the I/O standard. The IOL
current strength numbers shown are for a condition of a VOUT = VOL maximum,
where the VOL maximum is specified by the I/O standard. For 2.5-V
LVTTL/LVCMOS, the IOH condition is VOUT = 1.7 V and the IOL condition is
VOUT = 0.7 V.
Table 2–6. Programmable Drive Strength Note (1)
(Part 2 of 2)
I/O Standard
IOH/IOL Current Strength Setting (mA)
相關(guān)PDF資料
PDF描述
EPM2210F256A5N FLASH PLD, PBGA256
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EPM2210F324A4N FLASH PLD, PBGA324
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EPM2210GF256A3N FLASH PLD, PBGA256
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPM2210F256A5 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 204 IO RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM2210F256A5N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 204 IO RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM2210F256C3 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 204 IO RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM2210F256C3N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 204 IO RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM2210F256C4 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 204 IO RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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