參數(shù)資料
型號： EPM2210F256A4N
廠商： ALTERA CORP
元件分類： PLD
英文描述： FLASH PLD, PBGA256
封裝： 17 X 17 MM, 1 MM PITCH, LEAD FREE, FBGA-256
文件頁數(shù)： 56/108頁
文件大小： 1342K
代理商： EPM2210F256A4N
Altera Corporation
3–1
December 2007
Chapter 3. JTAG and
In-System Programmability
Introduction
This chapter discusses how to use the IEEE Standard 1149.1
Boundary-Scan Test (BST) circuitry in MAX II devices and includes the
following sections:
■
■
IEEE Std. 1149.1
(JTAG)
Boundary-Scan
Support
All MAX II devices provide Joint Test Action Group (JTAG)
boundary-scan test (BST) circuitry that complies with the IEEE Std.
1149.1-2001 specification. JTAG boundary-scan testing can only be
performed at any time after VCCINT and all VCCIO banks have been fully
powered and a tCONFIG amount of time has passed. MAX II devices can
also use the JTAG port for in-system programming together with either
the Quartus II software or hardware using Programming Object Files
(.pof), JamTM Standard Test and Programming Language (STAPL) Files
(.jam), or Jam Byte-Code Files (.jbc).
The JTAG pins support 1.5-V, 1.8-V, 2.5-V, or 3.3-V I/O standards. The
supported voltage level and standard are determined by the VCCIO of the
bank where it resides. The dedicated JTAG pins reside in Bank 1 of all
MAX II devices.
MAX II devices support the JTAG instructions shown in Table 3–1.
Table 3–1. MAX II JTAG Instructions (Part 1 of 2)
JTAG Instruction
Instruction Code
Description
SAMPLE/PRELOAD
00 0000 0101
Allows a snapshot of signals at the device pins to be captured
and examined during normal device operation, and permits an
initial data pattern to be output at the device pins.
EXTEST
00 0000 1111
Allows the external circuitry and board-level interconnects to
be tested by forcing a test pattern at the output pins and
capturing test results at the input pins.
BYPASS
11 1111 1111
Places the 1-bit bypass register between the TDI and TDO
pins, which allows the BST data to pass synchronously
through selected devices to adjacent devices during normal
device operation.
MII51003-1.5
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPM2210F256A5 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 204 IO RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM2210F256A5N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 204 IO RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM2210F256C3 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 204 IO RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM2210F256C3N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 204 IO RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM2210F256C4 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 204 IO RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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