Notes to tables: (1) These values are specified under the MAX 9000 d" />
參數(shù)資料
型號(hào)： EPM9560RC240-15
廠商： Altera
文件頁(yè)數(shù)： 29/46頁(yè)
文件大小： 0K
描述： IC MAX 9000 CPLD 560 240-RQFP
產(chǎn)品變化通告： Package Change 30/Jun/2010
標(biāo)準(zhǔn)包裝： 24
系列： Max® 9000
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1)： 15.0ns
電壓電源 - 內(nèi)部： 4.75 V ~ 5.25 V
邏輯元件/邏輯塊數(shù)目： 35
宏單元數(shù)： 560
門數(shù)： 12000
輸入/輸出數(shù)： 191
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 240-BFQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 240-RQFP（32x32）
包裝： 托盤
其它名稱： 544-2366
Altera Corporation
35
MAX 9000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
These values are specified under the MAX 9000 device recommended operating conditions, shown in Table 15 on
(2)
See Application Note 77 (Understanding MAX 9000 Timing) for more information on test conditions for tPD1 and tPD2
delays.
(3)
This parameter is a guideline that is sample-tested only. It is based on extensive device characterization. This
parameter applies for both global and array clocking as well as both macrocell and I/O cell registers.
(4)
Measured with a 16-bit loadable, enabled, up/down counter programmed in each LAB.
(5)
The tLPA parameter must be added to the tLOCAL parameter for macrocells running in low-power mode.
(6)
The tROW , tCOL, and tIOC delays are worst-case values for typical applications. Post-compilation timing simulation
or timing analysis is required to determine actual worst-case performance.
Power
Consumption
The supply power (P) versus frequency (fMAX) for MAX 9000 devices can
be calculated with the following equation:
P = PINT + PIO = ICCINT × VCC + PIO
The PIO value, which depends on the device output load characteristics
and switching frequency, can be calculated using the guidelines given in
depends on the switching frequency and the application logic.
The ICCINT value is calculated with the following equation:
ICCINT
= (A
× MC
TON) + [B × (MCDEV – MCTON)] + (C × MCUSED
× f
MAX × togLC)
Table 24. Interconnect Delays
Symbol
Parameter
Conditions
Speed Grade
Unit
-10
-15
-20
MinMax
t LOCAL
LAB local array delay
0.5
ns
t ROW
FastTrack row delay
0.9
1.4
2.0
ns
t COL
FastTrack column delay
0.9
1.7
3.0
ns
t DIN_D
Dedicated input data delay
4.0
4.5
5.0
ns
t DIN_CLK
Dedicated input clock delay
2.7
3.5
4.0
ns
t DIN_CLR
Dedicated input clear delay
4.5
5.0
5.5
ns
t DIN_IOC
Dedicated input I/O register
clock delay
2.5
3.5
4.5
ns
t DIN_IO
Dedicated input I/O register
control delay
5.5
6.0
6.5
ns
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPM9560RC240-15YY 制造商:Altera Corporation 功能描述:CPLD MAX 9000 Family 12K Gates 560 Macro Cells 117.6MHz CMOS Technology 5V 240-Pin RQFP 制造商:Altera Corporation 功能描述:CPLD MAX 9000 Family 12K Gates 560 Macro Cells 117.6MHz 5V 240-Pin RQFP
EPM9560RC240-20 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 9000 560 Macro 191 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM9560RC304-15 制造商:Altera Corporation 功能描述:IC MAX
EPM9560RI208-15 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
EPM9560RI208-20 制造商:Altera Corporation 功能描述:IC MAX
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