參數(shù)資料
型號: EPM9560RC240-15
廠商: Altera
文件頁數(shù): 4/46頁
文件大?。?/td> 0K
描述: IC MAX 9000 CPLD 560 240-RQFP
產(chǎn)品變化通告: Package Change 30/Jun/2010
標準包裝: 24
系列: Max® 9000
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 15.0ns
電壓電源 - 內(nèi)部: 4.75 V ~ 5.25 V
邏輯元件/邏輯塊數(shù)目: 35
宏單元數(shù): 560
門數(shù): 12000
輸入/輸出數(shù): 191
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 240-BFQFP 裸露焊盤
供應商設備封裝: 240-RQFP(32x32)
包裝: 托盤
其它名稱: 544-2366
12
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
The MAX+PLUS II Compiler automatically allocates as many as three sets
of up to five parallel expanders to macrocells that require additional
product terms. Each set of expanders incurs a small, incremental timing
delay (tPEXP). For example, if a macrocell requires 14 product terms, the
Compiler uses the five dedicated product terms within the macrocell and
allocates two sets of parallel expanders; the first set includes five product
terms and the second set includes four product terms, increasing the total
delay by 2
× t
PEXP.
Two groups of eight macrocells within each LAB (e.g., macrocells 1
through 8 and 9 through 16) form two chains to lend or borrow parallel
expanders. A macrocell borrows parallel expanders from lower-
numbered macrocells. For example, macrocell 8 can borrow parallel
expanders from macrocell 7, from macrocells 7 and 6, or from macrocells
7, 6, and 5. Within each group of 8, the lowest-numbered macrocell can
only lend parallel expanders and the highest-numbered macrocell can
only borrow them.
FastTrack Interconnect
In the MAX 9000 architecture, connections between macrocells and device
I/O pins are provided by the FastTrack Interconnect, a series of
continuous horizontal and vertical routing channels that traverse the
entire device. This device-wide routing structure provides predictable
performance even in complex designs. In contrast, the segmented routing
in FPGAs requires switch matrices to connect a variable number of
routing paths, increasing the delays between logic resources and reducing
performance. Figure 6 shows the interconnection of four adjacent LABs
with row and column interconnects.
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相關代理商/技術參數(shù)
參數(shù)描述
EPM9560RC240-15YY 制造商:Altera Corporation 功能描述:CPLD MAX 9000 Family 12K Gates 560 Macro Cells 117.6MHz CMOS Technology 5V 240-Pin RQFP 制造商:Altera Corporation 功能描述:CPLD MAX 9000 Family 12K Gates 560 Macro Cells 117.6MHz 5V 240-Pin RQFP
EPM9560RC240-20 功能描述:CPLD - 復雜可編程邏輯器件 CPLD - MAX 9000 560 Macro 191 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM9560RC304-15 制造商:Altera Corporation 功能描述:IC MAX
EPM9560RI208-15 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
EPM9560RI208-20 制造商:Altera Corporation 功能描述:IC MAX