參數(shù)資料
型號(hào)： EVAL-AD5522EBUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 3/64頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR 12X12MM AD5522
標(biāo)準(zhǔn)包裝： 1
主要目的： 測(cè)試與測(cè)量，參數(shù)測(cè)量單元（PMU）
已用 IC / 零件： AD5522
已供物品： 板
Data Sheet
AD5522
Rev. E | Page 11 of 64
Parameter
Min
Max
Unit
Test Conditions/Comments
Power Supply Sensitivity2
From dc to 1 kHz
ΔForced Voltage/ΔAVDD
80
dB
ΔForced Voltage/ΔAVSS
80
dB
ΔMeasured Current/ΔAVDD
85
dB
ΔMeasured Current/ΔAVSS
75
dB
ΔForced Current/ΔAVDD
75
dB
ΔForced Current/ΔAVSS
75
dB
ΔMeasured Voltage/ΔAVDD
85
dB
ΔMeasured Voltage/ΔAVSS
80
dB
ΔForced Voltage/ΔDVCC
90
dB
ΔMeasured Current/ΔDVCC
90
dB
ΔForced Current/ΔDVCC
90
dB
ΔMeasured Voltage/ΔDVCC
90
dB
1
Typical specifications are at 25°C and nominal supply, ±15.25 V, unless otherwise noted.
2
Guaranteed by design and characterization; not production tested. Tempco values are mean and standard deviation, unless otherwise noted.
TIMING CHARACTERISTICS
AVDD ≥ 10 V, AVSS ≤ 5 V, |AVDD AVSS| ≥ 20 V and ≤ 33 V, DVCC = 2.3 V to 5.25 V, VREF = 5 V, TJ = 25°C to 90°C, unless
otherwise noted.
Table 2. SPI Interface
Parameter 1, 2, 3
DVCC, Limit at TMIN, TMAX
Unit
Description
2.3V to 2.7V
2.7V to 3.6V
4.5V to 5.25V
tWRITE4
1030
735
ns min
Single channel update cycle time (X1 register write)
950
655
ns min
Single channel update cycle time (any other register write)
t1
30
20
ns min
SCLK cycle time
t2
8
ns min
SCLK high time
t3
8
ns min
SCLK low time
t4
10
ns min
SYNC falling edge to SCLK falling edge setup time
150
ns min
Minimum SYNC high time in write mode after X1 register
write (one channel)
70
ns min
Minimum SYNC high time in write mode after any
other register write
t6
10
5
ns min
29th SCLK falling edge to SYNC rising edge
t7
5
ns min
Data setup time
t8
9
7
4.5
ns min
Data hold time
t9
120
75
55
ns max
SYNC rising edge to BUSY falling edge
t10
BUSY pulse width low for X1 and some PMU register writes;
1 DAC X1
1.65
s max
2 DAC X1
2.3
s max
3 DAC X1
2.95
s max
4 DAC X1
3.6
s max
Other Registers
270
ns max
System control register/PMU registers
t11
20
ns min
29th SCLK falling edge to LOAD falling edge
t12
20
ns min
LOAD pulse width low
t13
150
ns min
BUSY rising edge to FOHx output response time
t14
0
ns min
BUSY rising edge to LOAD falling edge
t15
100
ns max
LOAD falling edge to FOHx output response time
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