參數(shù)資料
型號(hào)： EVAL-AD5522EBUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 57/64頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR 12X12MM AD5522
標(biāo)準(zhǔn)包裝： 1
主要目的： 測(cè)試與測(cè)量，參數(shù)測(cè)量單元（PMU）
已用 IC / 零件： AD5522
已供物品： 板
AD5522
Data Sheet
Rev. E | Page 60 of 64
Table 39. ADCs and ADC Drivers Suggested For Use with AD55221
Part No.
Resolution
Sample
Rate
Ch. No.
AIN Range
Interface
ADC Driver
Multiplexer2
Package
16
250 kSPS
1
0 V to VREF
Serial, SPI
MSOP,
LFCSP
16
500 kSPS
1
0 V to VREF
Serial, SPI
MSOP,
LFCSP
16
500 kSPS
1
VREF to +VREF
Serial, SPI
MSOP,
LFCSP
16
250 kSPS
1
Bipolar 10 V, Bipolar
5 V, Unipolar 10 V,
Unipolar 5 V
Serial/Parallel
LFCSP,
LQFP
16
1 MSPS
4
0 V to 5 V
Serial/Parallel
1
Subset of the possible ADCs suitable for use with the AD5522. Visit www.analog.com for more options.
2
For purposes of sharing an ADC among multiple PMU channels. Note that the multiplexer is not absolutely necessary because the AD5522 MEASOUTx path has a tri-
state mode per channel.
3
Do not allow the MEASOUTx output range to exceed the analog input (AIN) range of the ADC.
POWER SUPPLY DECOUPLING
Careful consideration of the power supply and ground return
layout helps to ensure the rated performance. Design the
printed circuit board (PCB) on which the AD5522 is mounted
so that the analog and digital sections are separated and
confined to certain areas of the board. If the AD5522 is in a
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
Establish the star ground point as close as possible to the device.
For supplies with multiple pins (AVSS and AVDD), it is
recommended that these pins be tied together and that each
supply be decoupled only once.
The AD5522 should have ample supply decoupling of 10 F
in parallel with 0.1 F on each supply located as close to the
package as possible, ideally right up against the device. The
10 F capacitors are the tantalum bead type. The 0.1 F capac-
itors should have low effective series resistance (ESR) and low
effective series inductance (ESL)—typical of the common
ceramic types that provide a low impedance path to ground at
high frequencies—to handle transient currents due to internal
logic switching.
Avoid running digital lines under the device because they can
couple noise onto the device. However, allow the analog ground
plane to run under the AD5522 to avoid noise coupling (applies
only to the package with paddle up). The power supply lines of
the AD5522 should use as large a trace as possible to provide
low impedance paths and reduce the effects of glitches on the
power supply line. Fast switching digital signals should be
shielded with digital ground to avoid radiating noise to other
parts of the board, and they should never be run near the refer-
ence inputs. It is essential to minimize noise on all VREF lines.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other to
reduce the effects of feedthrough through the board. As is the
case for all thin packages, care must be taken to avoid flexing
the package and to avoid a point load on the surface of this
package during the assembly process.
Also, note that the exposed paddle of the AD5522 is connected
to the negative supply, AVSS.
POWER SUPPLY SEQUENCING
When the supplies are connected to the AD5522, it is important
that the AGND and DGND pins be connected to the relevant
ground planes before the positive or negative supplies are applied.
This is the only power sequencing requirement for this device.
TYPICAL APPLICATION FOR THE AD5522
Figure 59 shows the AD5522 used in an ATE system. The device
can be used as a per-pin parametric unit to speed up the rate at
which testing can be done.
The central PMU (shown in the block diagram) is usually a
highly accurate PMU and is shared among a number of pins
in the tester. In general, many discrete levels are required in an
ATE system for the pin drivers, comparators, clamps, and active
loads. DAC devices such as the AD537x family offer a highly
integrated solution for a number of these levels.
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