AVDD = V
參數(shù)資料
型號(hào): EVAL-AD5755-1SDZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 52/52頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD5755-1
視頻文件: AD5755: 16-Bit Multi-Channel, Voltage and Current Output DAC
標(biāo)準(zhǔn)包裝: 1
DAC 的數(shù)量: 4
位數(shù): 16
數(shù)據(jù)接口: 串行
設(shè)置時(shí)間: 11µs
DAC 型: 電流/電壓
工作溫度: -40°C ~ 105°C
已供物品:
已用 IC / 零件: *
Data Sheet
AD5755-1
Rev. E | Page 9 of 52
TIMING CHARACTERISTICS
AVDD = VBOOST_x = 15 V; AVSS = 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND =
GNDSWx = 0 V; REFIN = 5 V; voltage outputs: RL = 1 k, CL = 220 pF; current outputs: RL = 300 ; all specifications TMIN to TMAX, unless
otherwise noted.
Table 3.
Parameter1, 2, 3
Limit at T
MIN, TMAX
Unit
Description
t
1
33
ns min
SCLK cycle time
t
2
13
ns min
SCLK high time
t
3
13
ns min
SCLK low time
t
4
13
ns min
SYNC falling edge to SCLK falling edge setup time
t
5
13
ns min
24th/32nd SCLK falling edge to SYNC rising edge (see Figure 78)
t
6
198
ns min
SYNC high time
t
7
5
ns min
Data setup time
t
8
5
ns min
Data hold time
t
9
20
s min
SYNC rising edge to LDAC falling edge (all DACs updated or any channel has
digital slew rate control enabled)
5
s min
SYNC rising edge to LDAC falling edge (single DAC updated)
t
10
ns min
LDAC pulse width low
t
11
500
ns max
LDAC falling edge to DAC output response time
t
12
s max
DAC output settling time
t
13
10
ns min
CLEAR high time
t
14
5
s max
CLEAR activation time
t
15
40
ns max
SCLK rising edge to SDO valid
t
16
21
s min
SYNC rising edge to DAC output response time (LDAC = 0) (all DACs updated)
5
s min
SYNC rising edge to DAC output response time (LDAC = 0) (single DAC updated)
t
17
500
ns min
LDAC falling edge to SYNC rising edge
t
18
800
ns min
RESET pulse width
t
20
s min
SYNC high to next SYNC low (digital slew rate control enabled) (all DACs updated)
5
s min
SYNC high to next SYNC low (digital slew rate control disabled) (single DAC
updated)
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with t
R = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.
4 This specification applies if LDAC is held low during the write cycle; otherwise, see t
9.
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