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參數(shù)資料
| 型號： | EVAL-AD7266EDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7266 A/D CONV |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 2M |
| 數(shù)據(jù)接口： | SPI?、QSPI?、MICROWIRE? 和 DSP |
| 輸入范圍： | 0 ~ 5 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 9mW @ 3V，27mW @ 5V |
| 工作溫度： | -40°C ~ 125°C |
| 已用 IC / 零件： | AD7266 |
| 已供物品： | 板 |
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AD7266
Rev. B | Page 5 of 28
TIMING SPECIFICATIONS
AVDD = DVDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, internal/external reference = 2.5 V, TA = TMAX to TMIN, unless otherwise noted1.
Table 2.
Parameter
Limit at TMIN, TMAX
Unit
Description
1
MHz min
TA = 40°C to +85°C
4
MHz min
TA > 85°C to 125°C
32
MHz max
tCONVERT
14 × tSCLK
ns max
tSCLK = 1/fSCLK
437.5
ns max
fSCLK = 32 MHz, VDD = 5 V, fSAMPLE = 2 MSPS
583.3
ns max
fSCLK = 24 MHz, VDD = 3 V, fSAMPLE = 1.5 MSPS
tQUIET
30
ns min
Minimum time between end of serial read and next falling edge of CS
t2
15/20
ns min
VDD = 5 V/3 V, CS to SCLK setup time, TA = 40°C to +85°C
20/30
ns min
VDD = 5 V /3 V, CS to SCLK setup time, TA > 85°C to 125°C
t3
15
ns max
Delay from CS until DOUTA and DOUTB are three-state disabled
36
ns max
Data access time after SCLK falling edge, VDD = 3 V
27
ns max
Data access time after SCLK falling edge, VDD = 5 V
t5
0.45 tSCLK
ns min
SCLK low pulse width
t6
0.45 tSCLK
ns min
SCLK high pulse width
t7
10
ns min
SCLK to data valid hold time, VDD = 3 V
5
ns min
SCLK to data valid hold time, VDD = 5 V
t8
15
ns max
CS
rising edge to DOUTA, DOUTB, high impedance
t9
30
ns min
CS
rising edge to falling edge pulse width
t10
5
ns min
SCLK falling edge to DOUTA, DOUTB, high impedance
35
ns max
SCLK falling edge to DOUTA, DOUTB, high impedance
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See Serial
2 Minimum SCLK for specified performance; with slower SCLK frequencies, performance specifications apply typically.
3 The time required for the output to cross 0.4 V or 2.4 V.
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