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參數(shù)資料
| 型號： | EVAL-AD7732EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7732 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 15.4k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±10 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 85mW @ 3V |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7732 |
| 已供物品： | 板，纜線，CD |
| 相關(guān)產(chǎn)品： | AD7732BRUZ-REEL7-ND - IC ADC 24BIT 2CH SIG-DEL 28TSSOP AD7732BRUZ-REEL-ND - IC ADC 24BIT 2CH SIG-DEL 28TSSOP AD7732BRUZ-ND - IC ADC 24BIT 2-CH 28-TSSOP AD7732BRU-ND - IC ADC 24BIT 2-CH 28-TSSOP |
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AD7732
Rev. A | Page 23 of 32
Reset
The AD7732 can be reset by the RESET pin or by writing a reset
sequence to the AD7732 serial interface.
The reset sequence is N × 0 + 32 × 1, which could be the data
sequence 00h + FFh + FFh + FFh + FFh in a byte-oriented
interface. The AD7732 also features a power-on reset with a
trip point of 2 V and goes to the defined default state after
power-on.
It is the system designer’s responsibility to prevent an unwanted
write operation to the AD7732. The unwanted write operation
could happen when a spurious clock appears on the SCLK while
the CS pin is low. It should be noted that on system power-on, if
the AD7732 interface signals are floating or undefined, the part
can be inadvertently configured into an unknown state. This
could be easily overcome by initiating either a hardware reset
event or a 32 ones reset sequence as the first step in the system
configuration.
Access the AD7732 Registers
All communications to the part start with a write operation to
the communications register followed by either reading or
writing the addressed register.
In a simultaneous read-write interface (such as SPI), write 0 to
the AD7732 while reading data.
Figure 16 shows the AD7732 interface read sequence for the
ADC status register.
DIN
SCLK
CS
DOUT
WRITE
COMMUNICATIONS
REGISTER
READ
ADC STATUS
REGISTER
Figure 16. Serial Interface Signals—Registers Access
Single Conversion and Reading Data
When the mode register is being written, the ADC status byte is
cleared and the RDY pin goes high, regardless of its previous
state. When the single conversion command is written to the
mode register, the ADC starts the conversion on the channel
selected by the address of the mode register. After the
conversion is completed, the data register is updated, the mode
register is changed to idle mode, the relevant RDY bit is set,
and the RDY pin goes low. The RDY bit is reset and the RDY
pin returns high when the relevant channel data register is
being read.
Figure 17 shows the digital interface signals executing a single
conversion on Channel 0, waiting for the RDY pin to go low,
and reading the Channel 0 data register.
DIN
SCLK
CS
DOUT
WRITE
COMMUNICATIONS
REGISTER
WRITE
MODE
REGISTER
RDY
CONVERSION TIME
READ DATA REGISTER
38h
40h
48h
(00h)
DATA
WRITE
COMMUNICATIONS
REGISTER
Figure 17. Serial Interface Signals—Single Conversion Command and 16-Bits Data Reading
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