參數(shù)資料
型號： EVAL-AD7732EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 4/32頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD7732
標準包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 15.4k
數(shù)據(jù)接口： 串行
輸入范圍： ±10 V
在以下條件下的電源（標準）： 85mW @ 3V
工作溫度： -40°C ~ 105°C
已用 IC / 零件： AD7732
已供物品： 板，纜線，CD
相關(guān)產(chǎn)品： AD7732BRUZ-REEL7-ND - IC ADC 24BIT 2CH SIG-DEL 28TSSOP
AD7732BRUZ-REEL-ND - IC ADC 24BIT 2CH SIG-DEL 28TSSOP
AD7732BRUZ-ND - IC ADC 24BIT 2-CH 28-TSSOP
AD7732BRU-ND - IC ADC 24BIT 2-CH 28-TSSOP
AD7732
Rev. A | Page 12 of 32
PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD7732
BIAS0(+)
AIN0(+)
AIN1(+)
BIAS1(+)
RB
RA
SYNC/P1
SCLK
MCLKIN
CS
P0
AVDD
RESET
BIAS0(–)
AIN0(–)
AIN1(–)
BIAS1(–)
RC
RD
REFIN(+)
DGND
DVDD
DIN
DOUT
REFIN(–)
AGND
RDY
MCLKOUT
Figure 11. 28-Lead TSSOP
P0
SYNC/P1
AIN0(+)
AIN1(+)
AIN0(–)
BIAS0(+)
BIAS0(–)
AIN1(–)
BIAS1(+)
BIAS1(–)
RA
RB
RC
RD
SCLK
DIN
DOUT
CS
RESET
RDY
DGND
MCLKIN
MCLKOUT
AGND AVDD
DVDD
AVDD
DVDD
7R
R=15.5k
Ω
2R
R
7R
2R
BUFFER
REFERENCE
DETECT
REFIN(–)
REFIN(+)
AD7732
24-BIT
ΣΔ ADC
SERIAL
INTERFACE
CONTROL
LOGIC
CLOCK
GENERATOR
CALIBRATION
CIRCUITRY
I/O PORT
MUX
Figure 12. Block Diagram
Table 10. Pin Function Descriptions—28-Lead TSSOP
Pin No.
Mnemonic
Description
1
SCLK
Serial Clock. Schmitt triggered logic input. An external serial clock is applied to this input
to transfer serial data to or from the AD7732.
2
MCLKIN
Master Clock Signal for the ADC. This can be provided in the form of a crystal/resonator
or external clock. A crystal/resonator can be tied across the MCLKIN and MCLKOUT pins.
Alternatively, the MCLKIN pin can be driven with a CMOS compatible clock and
MCLKOUT left unconnected.
3
MCLKOUT
When the master clock for the device is a crystal/resonator, the crystal/resonator is
connected between MCLKIN and MCLKOUT. If an external clock is applied to the
MCLKIN, MCLKOUT provides an inverted clock signal or can be switched off to reduce
the device power consumption. MCLK OUT is capable of driving one CMOS load.
4
CS
Chip Select. Active low Schmitt triggered logic input with an internal pull-up resistor.
With this input hardwired low, the AD7732 can operate in its 3-wire interface mode
using SCLK, DIN, and DOUT. CS can be used to select the device in systems with more
than one device on the serial bus. It can also be used as an 8-bit frame
synchronization signal.
5
RESET
Schmitt Triggered Logic Input. Active low input that resets the control logic, interface
logic, digital filter, analog modulator, and all on-chip registers of the part to power-on
status. Effectively, everything on the part except the clock oscillator is reset when the
RESET pin is exercised.
6
AVDD
Analog Positive Supply Voltage. 5 V to AGND nominal.
7
P0
Digital Input/Output. The pin direction is determined by the P0 DIR bit; the digital
value can be read/written as the P0 bit in the I/O port register. The digital voltage is
referenced to analog supplies. When configured as an input, the pin should be tied
high or low.
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