參數(shù)資料
型號： EVAL-AD7732EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 20/32頁
文件大小： 0K
描述： BOARD EVAL FOR AD7732
標準包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 15.4k
數(shù)據(jù)接口： 串行
輸入范圍： ±10 V
在以下條件下的電源（標準）： 85mW @ 3V
工作溫度： -40°C ~ 105°C
已用 IC / 零件： AD7732
已供物品： 板，纜線，CD
相關(guān)產(chǎn)品： AD7732BRUZ-REEL7-ND - IC ADC 24BIT 2CH SIG-DEL 28TSSOP
AD7732BRUZ-REEL-ND - IC ADC 24BIT 2CH SIG-DEL 28TSSOP
AD7732BRUZ-ND - IC ADC 24BIT 2-CH 28-TSSOP
AD7732BRU-ND - IC ADC 24BIT 2-CH 28-TSSOP
AD7732
Rev. A | Page 27 of 32
Analog Input’s Extended Voltage Range
The AD7732 output data code span corresponds to the nominal
input voltage range. The ADC is functional outside the nominal
input voltage range, but the performance might degrade. The
sigma-delta modulator was designed to fully cover a ±11.6 V
differential input voltage; outside this range, the performance
might degrade more rapidly. The adjacent channels are not
affected by up to ±16.5 V absolute analog input voltage
When the CLAMP bit in the mode register is set to 1, the
channel data register will be digitally clamped to either all 0s or
all 1s when the analog input voltage goes outside the nominal
input voltage range.
As shown in Table 16 and Table 17, when CLAMP = 0, the data
reflects the analog input voltage outside the nominal voltage
range. In this case, the SIGN and OVR bits in the channel status
register should be considered along with the data register value
to decode the actual conversion result.
Note that the OVR bit in the channel status register is generated
digitally from the conversion result and indicates the sigma-
delta modulator (nominal) overrange. The OVR bit DOES NOT
indicate exceeding the AIN pin’s absolute voltage limits.
Table 16. Extended Input Voltage Range,
Nominal Voltage Range ±10 V, 16 Bits, CLAMP = 0
Input (V)
Data (hex)
SIGN
OVR
11.60039
147B
0
1
10.00061
0001
0
1
10.00031
0000
0
1
10.00000
FFFF
0
0.00031
8001
0
0.00000
8000
0
–0.00031
7FFF
1
0
–10.00000
0000
1
0
–10.00031
FFFF
1
–10.00061
FFFE
1
–11.60040
EB85
1
Table 17. Extended Input Voltage Range, Nominal
Voltage Range 0 V to +10 V, 16 Bits, CLAMP = 0
Input (V)
Data (hex)
SIGN
OVR
11.60006
28F5
0
1
10.00031
0001
0
1
10.00015
0000
0
1
10.00000
FFFF
0
0.00015
0001
0
0.00000
0000
0
–0.00015
0000
1
Chopping
With chopping enabled, the multiplexer repeatedly reverses the
ADC inputs. Every output data result is then calculated as an
average of two conversions, the first with the positive and the
second with the negative offset term included. This effectively
removes any offset error of the input buffer and sigma-delta
modulator.
However, chopping is applied only behind the input resistor
divider stage; therefore, chopping does not eliminate the offset
error and drifts caused by the resistors. Figure 24 shows the
channel signal chain with chopping enabled.
+
-
DIGITAL
INTERFACE
CHOP
fMCLK/2
BUFFER
MULTIPLEXER
DIGITAL
FILTER
SCALING
ARITHMETIC
(CALIBRATIONS)
OUTPUT DATA
AT THE SELECTED
DATA RATE
AI N(+)
AIN(–)
BIAS(+)
BI AS(–)
ΣΔ
MODULATOR
Figure 24. Channel Signal Chain Diagram with Chopping Enabled
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