參數(shù)資料
型號(hào): EVAL-AD7738EBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 13/28頁(yè)
文件大小: 0K
描述: BOARD EVAL FOR AD7738
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 1
位數(shù): 24
采樣率(每秒): 15.4k
數(shù)據(jù)接口: 串行
輸入范圍: ±2.5 V
在以下條件下的電源(標(biāo)準(zhǔn)): 85mW @ 5V
工作溫度: -40°C ~ 105°C
已用 IC / 零件: AD7738
已供物品:
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REV. 0
–20–
AD7738
DIGITAL INTERFACE DESCRIPTION
Hardware
The AD7738 serial interface can be connected to the host
device via the serial interface in several different ways.
The
CS pin can be used to select the AD7738 as one of several
circuits connected to the host serial interface. When the
CS is
high, the AD7738 ignores the SCLK and DIN signals and
the DOUT pin goes to the high impedance state. When the
CS
signal is not used, connect the
CS pin to DGND.
The
RDY pin can be either polled for high to low transition or
can drive the host device interrupt input to indicate that the
AD7738 has finished the selected operation and/or new data
from the AD7738 are available. The host system can also wait a
designated time after a given command is written to the device
before reading. Alternatively, the AD7738 status can be polled.
When the
RDY pin is not used in the system, it should be left as
an open circuit. (Note that the
RDY pin is always an active
digital output, i.e., never goes into a high impedance state).
The
RESET pin can be used to reset the AD7738. When not
used, connect this pin to DVDD.
The AD7738 interface can be reduced to just two wires con-
necting DIN and DOUT pins to a single bidirectional data line.
The second signal in this 2-wire configuration is the SCLK
signal. The host system should change the data line direction
with reference to the AD7738 timing specification (see the Bus
Relinquish Time in the Timing Characteristics). The AD7738
cannot operate in the Continuous Read mode in 2-wire serial
interface configuration.
All the digital interface inputs are Schmitt-Triggered. There-
fore, the AD7738 interface features higher noise immunity
and the AD7738 can be easily isolated from the host system via
optocouplers.
Figure 5 outlines some of the possible host device interfaces:
(a) SPI without using the
CS signal, (b) DSP interface, and
(c) 2-wire configuration.
Reset
The AD7738 can be reset by the
RESET pin or by writing a
reset sequence to the AD7738 serial interface. The reset
sequence is N
“0” + 32
“1”, which could be the data
sequence 00h + FFh + FFh + FFh + FFh in a byte oriented
interface. The AD7738 also features a power-on reset with a
trip point of 2 V and goes to the defined default state after
power on.
It is the system designer’s responsibility to prevent an unwanted
write operation to the AD7738. The unwanted write operation
could happen when a spurious clock appears on the SCLK
while the
CS pin is low. It should be noted that on system
power-on, if the AD7738 interface signals are floating or unde-
fined, the part can be inadvertently configured into an unknown
state. This could be easily overcome by initiating either a HW
reset event or a 32 ones reset sequence as the first step in the
system configuration.
SCLK
DIN
DOUT
CS
RDY
RESET
DGND
DVDD
AD7738
SCK
MOSI
MISO
INT
68HC11
SS
DVDD
SCLK
DIN
DOUT
CS
RDY
RESET
DVDD
AD7738
SCLK
DT
DR
INT
ADSP-2105
TFS
RFS
SCLK
DIN
DOUT
CS
RESET
DGND
DVDD
AD7738
P3.1/TXD
P3.0/RXD
8xC51
a.
b.
c.
Figure 5. AD7738 to Host Device Possible Interface
Access the AD7738 Registers
All communications to the part start with a write operation to
the Communications register followed by either reading or
writing the addressed register.
In a simultaneous read-write interface (such as SPI), write “0”
to the AD7738 while reading data.
Figure 6 shows the AD7738 interface read sequence for the
ADC Status register.
DIN
SCLK
CS
DOUT
WRITE
COMMUNICATIONS
REGISTER
READ
ADC STATUS
REGISTER
Figure 6. The Serial Interface Signals—Register Access
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