8 Bits, Read/Write Register, Address 28h–2Fh, Default Value 00h These registers are used to configur" />
參數(shù)資料
型號： EVAL-AD7738EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 9/28頁
文件大小： 0K
描述： BOARD EVAL FOR AD7738
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 15.4k
數(shù)據(jù)接口： 串行
輸入范圍： ±2.5 V
在以下條件下的電源（標(biāo)準(zhǔn)）： 85mW @ 5V
工作溫度： -40°C ~ 105°C
已用 IC / 零件： AD7738
已供物品： 板
相關(guān)產(chǎn)品： AD7738BRUZ-REEL7-ND - IC ADC 24BIT 8CH SIG-DEL 28TSSOP
AD7738BRUZ-REEL-ND - IC ADC 24BIT 8CH SIG-DEL 28TSSOP
AD7738BRUZ-ND - IC ADC 24BIT 8-CH 28-TSSOP
AD7738BRU-REEL7-ND - IC ADC 24BIT 8CH SIG-DEL 28TSSOP
AD7738BRU-ND - IC ADC 24BIT 8-CH 28-TSSOP
REV. 0
AD7738
–17–
Channel Setup Registers
8 Bits, Read/Write Register, Address 28h–2Fh, Default Value 00h
These registers are used to configure the selected channel, its input voltage range, and set up the corresponding Channel Status
register.
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mnemonic
BUF OFF
COM1
COM0
Stat. Opt.
ENABLE
RNG2
RNG1
RNG0
Default
0
Bit
Mnemonic
Description
7
BUF OFF
Buffer Off. If reset to 0, then internal buffer is enabled. Only operation with internal buffer enabled
is recommended.
6, 5
COM1, COM0 Analog Input Configuration. See Table XI.
4
Stat. Opt.
Status Option. When this bit is set to 1, the P1 bit in the Status Channel register will reflect the state
of the P1 pin. When this bit is reset to 0, the P1 bit in the Status Channel register bit will reflect
the channel corresponding RDY bit in the ADC Status register.
3
ENABLE
Channel Enable. Set this bit to 1 to enable the channel in the Continuous Conversion mode. A single
conversion will take place regardless of this bit value.
2–0
RNG2–0
The Channel Input Voltage Range. See Table XII.
Table XI.
COM1
COM0
COM1
COM0
Channel
0
1
0
AIN0–AINCOM
AIN0–AIN1
1
AIN1–AINCOM
AIN2–AIN3
2
AIN2–AINCOM
AIN4–AIN5
3
AIN3–AINCOM
AIN6–AIN7
4
AIN4–AINCOM
AIN0–AIN1
5
AIN5–AINCOM
AIN2–AIN3
6
AIN6–AINCOM
AIN4–AIN5
7
AIN7–AINCOM
AIN6–AIN7
Table XII.
Nominal Input
RNG2
RNG1
RNG0
Voltage Range
10
0
±2.5 V
10
10 V to +2.5 V
00
0
±1.25 V
00
10 V to +1.25 V
01
0
±0.625 V
01
10 V to +0.625 V
Channel Conversion Time Registers
8 Bits, Read/Write Register, Address 30h–37h, Default Value 91h
The Conversion Time registers enable or disable chopping and configure the digital filter for a particular channel.
This register value affects the conversion time, frequency response, and noise performance of the ADC.
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mnemonic
CHOP
FW (7-Bit Filter Word)
Default
1
11h
Bit
Mnemonic
Description
7
CHOP
Chop Enable Bit. Set to 1 to apply chopping mode for a particular channel.
6–0
FW
CHOP = 1, Single Conversion or Continuous Conversion with one channel enabled.
Conversion Time (
s) = (FW
128 + 248)/MCLK Frequency (MHz), the FW in range of 2 to 127.
CHOP = 1, Continuous Conversion with two or more channels enabled.
Conversion Time (
s) = (FW
128 + 249)/MCLK Frequency (MHz), the FW in range of 2 to 127.
CHOP = 0, Single Conversion or Continuous Conversion with one channel enabled.
Conversion Time (
s) = (FW
64 + 206)/MCLK Frequency (MHz), the FW in range of 3 to 127.
CHOP = 0, Single Conversion or Continuous Conversion with two or more channels enabled.
Conversion Time (
s) = (FW
64 + 207)/MCLK Frequency (MHz), the FW in range of 3 to 127.
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