參數(shù)資料
型號(hào)： EVAL-AD7738EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 22/28頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD7738
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 15.4k
數(shù)據(jù)接口： 串行
輸入范圍： ±2.5 V
在以下條件下的電源（標(biāo)準(zhǔn)）： 85mW @ 5V
工作溫度： -40°C ~ 105°C
已用 IC / 零件： AD7738
已供物品： 板
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REV. 0
AD7738
–3–
Parameter
Min
Typ
Max
Unit
Test Conditions/Comment
LOGIC INPUTS
SCLK, DIN,
CS, and RESET Inputs
Input Current
±1
A
Input Current
CS
±10
A
CS = AV
DD
–40
A
Internal Pull-Up Resistor
Input Capacitance
4
pF
VT+
1
1.4
2
V
DVDD = 5 V
VT–
1
0.8
1.4
V
DVDD = 5 V
VT+ – VT–
1
0.3
0.85
V
DVDD = 5 V
VT+
1
0.95
2
V
DVDD = 3 V
VT–
1
0.4
1.1
V
DVDD = 3 V
VT+ – VT–
1
0.3
0.85
V
DVDD = 3 V
MCLK IN Only
Input Current
±10
A
Input Capacitance
4
pF
VINL Input Low Voltage
0.8
V
DVDD = 5 V
VINH Input High Voltage
3.5
V
DVDD = 5 V
VINL Input Low Voltage
0.4
V
DVDD = 3 V
VINH Input High Voltage
2.5
V
DVDD = 3 V
LOGIC OUTPUTS
MCLKOUT
10, DOUT,
RDY
VOL Output Low Voltage
0.4
V
ISINK = 800
A, DVDD = 5 V
VOH Output High Voltage
4.0
V
ISOURCE = 200
A, DV
DD = 5 V
VOL Output Low Voltage
0.4
V
ISINK = 100
A, DV
DD = 3 V
VOH Output High Voltage
DVDD – 0.6
V
ISOURCE = 100
A, DV
DD = 3 V
Floating State Leakage Current
±1
A
Floating State Leakage Capacitance
3
pF
P1 INPUT
Levels Referenced to Analog Supplies
Input Current
±10
A
VINL Input Low Voltage
0.8
V
AVDD = 5 V
VINH Input High Voltage
3.5
V
AVDD = 5 V
P0, P1 OUTPUT
VOL Output Low Voltage
0.4
V
ISINK = 8 mA, TMAX = 70
°C, AV
DD = 5 V
0.4
V
ISINK = 5 mA, TMAX = 85
°C, AV
DD = 5 V
0.4
V
ISINK = 2.5 mA, TMAX = 105
°C, AV
DD = 5 V
VOH Output High Voltage
4.0
V
ISOURCE = 200
A, AV
DD = 5 V
POWER REQUIREMENTS
AVDD – AGND Voltage
4.75
5.25
V
DVDD – DGND Voltage
4.75
5.25
V
2.70
3.60
V
AVDD Current (Normal Mode)
13.6
16
mA
AVDD = 5 V
AVDD Current (Internal Buffer Off )
8.5
mA
AVDD = 5 V
DVDD Current (Normal Mode)
11
2.7
3
mA
DVDD = 5 V
DVDD Current (Normal Mode)
11
1.0
1.5
mA
DVDD = 3 V
AVDD + DVDD Current (Standby Mode)
12
80
AAV
DD = DVDD = 5 V
Power Dissipation (Normal Mode)
11
85
100
mW
Power Dissipation (Standby Mode)
12
500
WAV
DD = DVDD = 5 V
NOTES
1Specifications are not production tested, but guaranteed by design and/or characterization data at initial product release.
2Specifications before calibration. Channel System Calibration reduces these errors to the order of the noise.
3Applies after the Zero Scale and Full-Scale calibration. The Negative Full Scale error represents the remaining error after removing the offset and gain error.
4Specifications before calibration. ADC Zero Scale Self-Calibration or Channel Zero Scale System Calibration reduces this error to the order of the noise.
5The output data span corresponds to the Nominal (Typical) Input Voltage Range. Correct operation of the ADC is guaranteed within the specified min/max.
Outside the Nominal Input Voltage Range, the OVR bit in the Channel Status register is set and the Channel Data register value depends on CLAMP bit in the
Mode register. See the register description and circuit description for more details.
6If chopping is enabled or when switching between channels, there will be a dynamic current charging the capacitance of the multiplexer, capacitance of the pins,
and any additional capacitance connected to the MUXOUT. See the circuit description for more details.
7For specified performance. Part is functional with Lower V
REF
8Dynamic current charging the sigma-delta modulator input switching capacitor.
9Outside the specified calibration range, calibration is possible but the performance may degrade.
10These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load.
11With external MCLK, MCLKOUT disabled (CLKDIS bit set in the Mode register).
12External MCLKIN = 0 V or DV
DD, Digital Inputs = 0 V or DVDD, P0 and P1 = 0 V or AVDD.
Specifications are subject to change without notice.
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