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參數資料
| 型號： | EVAL-AD7785EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 13/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7785 |
| 標準包裝： | 1 |
| ADC 的數量： | 1 |
| 位數： | 20 |
| 采樣率（每秒）： | 470 |
| 數據接口： | 串行 |
| 輸入范圍： | ±VREF |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7785 |
| 已供物品： | 板，纜線，CD |
| 相關產品： | AD7785BRUZ-REEL-ND - IC ADC 20BIT 3CH LN LP 16-TSSOP AD7785BRUZ-ND - IC ADC 20BIT SIGMA-DELTA 16TSSOP |
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AD7785
Rev. 0 | Page 20 of 32
ADC CIRCUIT INFORMATION
OVERVIEW
The AD7785 is a low power ADC that incorporates a ∑-Δ
modulator, a buffer, reference, in-amp, and an on-chip digital
filter intended for the measurement of wide dynamic range, low
frequency signals such as those in pressure transducers, weigh
scales, and temperature measurement applications.
The part has three differential inputs that can be buffered or
unbuffered. The device can be operated with the internal 1.17 V
reference, or an external reference can be used. Figure 12 shows
the basic connections required to operate the part.
The output rate of the AD7785 (fADC) is user-programmable. The
allowable update rates, along with their corresponding settling
times, are listed in Table 14. Normal mode rejection is the major
function of the digital filter. Simultaneous 50 Hz and 60 Hz
rejection is optimized when the update rate equals 16.7 Hz or
less as notches are placed at both 50 Hz and 60 Hz with these
update rates (see Figure 14.)
The AD7785 uses slightly different filter types, depending on
the output update rate so that the rejection of quantization
noise and device noise is optimized. When the update rate is
from 4.17 Hz to 12.5 Hz, a Sinc3 filter, along with an averaging
filter, is used. When the update rate is from 16.7 Hz to 39 Hz, a
modified Sinc3 filter is used. This filter provides simultaneous
50 Hz/60 Hz rejection when the update rate equals 16.7 Hz. A
Sinc4 filter is used when the update rate is from 50 Hz to
242 Hz. Finally, an integrate-only filter is used when the update
rate equals 470 Hz.
different filter types for several update rates.
06
72
1-
01
2
DOUT/RDY
DIN
SCLK
CS
DVDD
SERIAL
INTERFACE
AND
CONTROL
LOGIC
Σ-Δ
ADC
AD7785
AIN2(+)
REFIN(+)
REFIN(–)
AIN2(–)
AVDD
GND
MUX
BAND GAP
REFERENCE
INTERNAL
CLOCK
CLK
GND
AVDD
IN-AMP
BUF
REFIN(+) REFIN(–)
VBIAS
AIN1(+)
AIN1(–)
R
THERMOCOUPLE
JUNCTION
C
RREF
IOUT2
Figure 12. Basic Connection Diagram
0
–20
–40
–60
–80
–100
0
120
100
80
60
40
20
06
72
1-
01
3
FREQUENCY (Hz)
(dB
)
Figure 13. Filter Profile with Update Rate = 4.17 Hz
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