參數(shù)資料
型號: EVAL-AD7879-1EBZ
廠商: Analog Devices Inc
文件頁數(shù): 24/41頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD7879-1
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,觸摸屏控制器
嵌入式:
已用 IC / 零件: AD7879-1
主要屬性: 4 線電阻式觸控屏控制器,I²C 和 SPI 接口
次要屬性: 圖形用戶界面,USB 接口
已供物品: 板,線纜,CD,觸控屏
AD7879/AD7889
Rev. C | Page 29 of 40
TEMP
MASK
AUX/
VBAT
MASK
INT
MODE
GPIO
ALERT
AUX/
VBAT
LOW
AUX/
VBAT
HIGH
TEMP
HIGH
X+
Y+
Z1
Z2
AUX
VBAT TEMP
NOT
USED
07667-
031
0
15
TEMP
LOW
Figure 32. Control Register 3
CONTROL REGISTER 3
Control Register 3 (Address 0x03) includes the interrupt
register (Bits[15:8]) and the sequencer bits (Bits[7:0]).
Sequencer (Control Register 3, Bits[7:0])
The sequencer bits control which channels are converted during
a conversion sequence in both slave mode and master mode.
To include a measurement in a sequence, the relevant bit must
be set in the sequence. Setting Bit 7 includes a measurement on
the X+ channel (Y position). Setting Bit 6 includes a measure-
ment on the Y+ channel (X position), and so on (see Table 14).
Figure 32 illustrates the correspondence between the bits in
Control Register 3 and the various measurements. Bit 0 is
not used.
SLAVE MODE
CONVERSION
SEQUENCE
TIMER = 00?
START TIMER
WAIT FOR TIMER
SINGLE
CONVERSION
MASTER MODE
WAIT FOR
FIRST TOUCH
CONVERSION
SEQUENCE
SCREEN
TOUCHED?
TIMER = 00?
START TIMER
WAIT FOR TIMER
SCREEN
TOUCHED?
IDLE
ADC MODE?
10
YES
NO
YES
NO
11
00
07667-
032
01
Figure 33. Conversion Modes
FCD
REQ’D?
WAIT FOR
ACQUISITION
ACQ
SET CHANNEL
CONVERT DATA
AVERAGE DATA
TRANSFER DATA
TO REGISTERS
SET ALERT AND
INTERRUPT
1MEDIAN # MEANS MEDIAN
FILTER SIZE.
RANK NEW
DATA
(WAIT tSORT)
MEDIAN
# OF SAMPLES
TAKEN?1
NO
YES
07667-
033
START OF
CONVERSION
SEQUENCE
FCD
MAV FILTER
ENABLED
?
OUT-OF-
LIMIT?
END OF
SEQUENCE
?
YES
NO
YES
NO
Figure 34. Conversion Sequence
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