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參數(shù)資料
型號: EVAL-AD7879-1EBZ
廠商: Analog Devices Inc
文件頁數(shù): 37/41頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD7879-1
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,觸摸屏控制器
嵌入式:
已用 IC / 零件: AD7879-1
主要屬性: 4 線電阻式觸控屏控制器,I²C 和 SPI 接口
次要屬性: 圖形用戶界面,USB 接口
已供物品: 板,線纜,CD,觸控屏
AD7879/AD7889
Rev. C | Page 4 of 40
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER REQUIREMENTS
VCC
1.6
2.6
3.6
V
Specified performance.
ICC
Digital inputs = 0 V or VCC.
Converting Mode
480
650
A
ADC on, PM = 10.
Static
406
A
ADC and temperature sensor are off; the
reference and oscillator are on; PM = 01
or 11.
Shutdown Mode
0.5
6
A
PM = 00.
1
See the Terminology section.
2
Guaranteed by characterization; not production tested.
3
Sample tested at 25°C to ensure compliance.
SPI TIMING SPECIFICATIONS (AD7879/AD7889)
VCC = 1.6 V to 3.6 V, TA = 40°C to +85°C, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input signals are
specified with tR = tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.4 V.
Table 2.
Parameter1
Limit
Unit
Description
fSCL
5
MHz max
t1
5
ns min
CS falling edge to first SCL falling edge
t2
20
ns min
SCL high pulse width
t3
20
ns min
SCL low pulse width
t4
15
ns min
DIN setup time
t5
15
ns min
DIN hold time
t6
20
ns max
DOUT access time after SCL falling edge
t7
16
ns max
CS rising edge to DOUT high impedance
t8
15
ns min
SCL rising edge to CS high
1
Guaranteed by design; not production tested.
CS
SCL
DIN
DOUT
t1
1
16
15
MSB
LSB
2
3
MSB
LSB
1
2
15
16
t2
t4
t5
t3
t6
t7
t8
07667-
002
Figure 2. Detailed SPI Timing Diagram
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