Data Sheet
AD9832
Rev. E | Page 3 of 28
SPECIFICATIONS
VDD = +5 V ± 5%; AGND = DGND = 0 V; TA = TMIN to TMAX; REFIN = REFOUT; RSET = 3.9 k; RLOAD = 300 for IOUT, unless otherwise
Table 1.
AD9832B
Unit
Test Conditions/Comments
SIGNAL DAC SPECIFICATIONS
Resolution
10
Bits
Update Rate (fMAX)
25
MSPS nom
IOUT Full Scale
4
mA nom
4.5
mA max
Output Compliance
1.35
V max
3 V power supply
DC Accuracy
Integral Nonlinearity
±1
LSB typ
Differential Nonlinearity
±0.5
LSB typ
Dynamic Specifications
Signal-to-Noise Ratio
50
dB min
fMCLK = 25 MHz, fOUT = 1 MHz
Total Harmonic Distortion
53
dBc max
fMCLK = 25 MHz, fOUT = 1 MHz
Spurious-Free Dynamic Range (SFDR)
3fMCLK = 6.25 MHz, fOUT = 2.11 MHz
Narrow Band (±50 kHz)
72
dBc min
5 V power supply
70
dBc min
3 V power supply
Wideband (±2 MHz)
50
dBc min
Clock Feedthrough
60
dBc typ
1
ms typ
Power-Down Option
Yes
VOLTAGE REFERENCE
Internal Reference @ 25°C
1.21
V typ
TMIN to TMAX
1.21 ± 7%
V min/V max
REFIN Input Impedance
10
M typ
Reference Temperature Coefficient (TC)
100
ppm/°C typ
REFOUT Output Impedance
300
typ
LOGIC INPUTS
Input High Voltage, VINH
VDD 0.9
V min
Input Low Voltage, VINL
0.9
V max
Input Current, IINH
10
A max
Input Capacitance, CIN
10
pF max
POWER SUPPLIES
AVDD
2.97/5.5
V min/V max
DVDD
2.97/5.5
V min/V max
IAA
5
mA max
5 V power supply
IDD
2.5 + 0.4/MHz
mA typ
5 V power supply
15
mA max
3 V power supply
24
mA max
5 V power supply
Low Power Sleep Mode
350
A max
1
Operating temperature range is 40°C to +85°C.
2
100% production tested.
3
fMCLK = 6.25 MHz, frequency word = 0x5671C71C, and fOUT = 2.11 MHz.
4
Se
e Figure 13. To reduce the wake-up time at low power supplies and low temperature, the use of an external reference is suggested.
5
Measured with the digital inputs static and equal to 0 V or DVDD. The AD9832 is tested with a capacitive load of 50 pF. The part can operate with higher capacitive
loads, but the magnitude of the analog output will be attenuated. For example, a 5 MHz output signal is attenuated by 3 dB when the load capacitance equals 85 pF.