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參數(shù)資料
| 型號： | EVAL-AD9832SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/28頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9832 |
| 標準包裝： | 1 |
| 系列： | * |
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Data Sheet
AD9832
Rev. E | Page 11 of 28
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale, a point 0.5 LSB
below the first code transition (000 . . . 00 to 000 . . . 01) and full
scale, a point 0.5 LSB above the last code transition (111 . . . 10
to 111 . . . 11). The error is expressed in LSBs.
Differential Nonlinearity
This is the difference between the measured and ideal 1 LSB
change between two adjacent codes in the DAC.
Signal-to-Noise-and-Distortion Ratio
It is measured signal to noise at the output of the DAC. The
signal is the rms magnitude of the fundamental. Noise is the
rms sum of all the nonfundamental signals up to half the
sampling frequency (fMCLK/2) but excluding the dc component.
The signal-to-noise-and-distortion ratio is dependent on the
number of quantization levels used in the digitization process;
the more levels, the smaller the quantization noise. The theoretical
signal-to-noise-and-distortion ratio for a sine wave input is
Signal-to-Noise-and-Distortion = (6.02N + 1.76) dB
where N is the number of bits. Thus, for an ideal 10-bit converter,
the signal-to-noise-and-distortion ratio = 61.96 dB.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the rms value of
the fundamental. For the AD9832, THD is defined as
1
2
6
2
5
2
4
2
3
2
log
20
V
THD
+
=
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonic.
Output Compliance
The output compliance refers to the maximum voltage that can
be generated at the output of the DAC to meet the specifications.
When voltages greater than those specified for the output
compliance are generated, the AD9832 may not meet the
specifications listed in the data sheet.
Spurious-Free Dynamic Range (SFDR)
Along with the frequency of interest, harmonics of the fundamental
frequency and images of the MCLK frequency are present at the
output of a DDS device. SFDR refers to the largest spur or harmonic
present in the band of interest. The wide-band SFDR gives the
magnitude of the largest harmonic or spur relative to the magnitude
of the fundamental frequency in the bandwidth ±2 MHz about
the fundamental frequency. The narrowband SFDR gives the
attenuation of the largest spur or harmonic in a bandwidth of
±50 kHz about the fundamental frequency.
Clock Feedthrough
There is feedthrough from the MCLK input to the analog output.
Clock feedthrough refers to the magnitude of the MCLK signal
relative to the fundamental frequency in the output spectrum of
the AD9832.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD9833EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:+2.5 V to +5.5 V, 25 MHz Low Power CMOS Complete DDS |
| EVAL-AD9833EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For IC Programmable Waveform Generator 制造商:Analog Devices 功能描述:PROGRAMMABLE WAVEFORM GENERATOR - Bulk |
| EVAL-AD9833SDZ | 功能描述:BOARD EVAL FOR AD9833 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:- 主要目的:數(shù)字電位器 嵌入式:- 已用 IC / 零件:AD5258 主要屬性:- 次要屬性:- 已供物品:板 相關產品:AD5258BRMZ1-ND - IC POT DGTL I2C1K 64P 10MSOPAD5258BRMZ10-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ100-ND - IC POT DGTL I2C 100K 64P 10MSOPAD5258BRMZ50-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ1-R7-ND - IC POT DGTL I2C 1K 64P 10MSOPAD5258BRMZ10-R7-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ50-R7-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ100-R7-ND - IC POT DGTL I2C 100K 64P 10MSOP |
| EVAL-AD9834EB | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
| EVAL-AD9834EBZ | 制造商:Analog Devices 功能描述:Evaluation Kit For 20 MW Power, 2.3 V To 5.5 V, 75 MHz Complete DDS 制造商:Analog Devices 功能描述:EVAL KIT FOR 20 MW PWR, 2.3V TO 5.5 V, 75 MHZ COMPLETE DDS - Bulk |
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