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| 型號： | EVAL-AD9832SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9832 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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Data Sheet
AD9832
Rev. E | Page 15 of 28
When writing to a phase register, the 4 MSBs of the 16-bit word
loaded into the data register should be zero (the phase registers
are 12 bits wide).
To alter the entire contents of a frequency register, four write
operations are needed. However, the 16 MSBs of a frequency
word are contained in a separate register to the 16 LSBs.
Therefore, the 16 MSBs of the frequency word can be altered
independent of the 16 LSBs.
Table 9. Commands
C3
C2
C1
C0
Command
0
Write 16 phase bits (present 8 bits + 8 bits
in the defer register) to selected PHASEx REG.
0
1
Write 8 phase bits to the defer register.
0
1
0
Write 16 frequency bits (present 8 bits +
8 bits in the defer register) to selected the
FREQx REG.
0
1
Write 8 frequency bits to the defer register.
0
1
0
Bit D9 (PSEL0) and Bit D10 (PSEL1) are used
to select the PHASEx REG when SELSRC = 1.
When SELSRC = 0, the PHASEx REG is
selected using the PSEL0 and PSEL1 pins.
0
1
0
1
Bit D11 is used to select the FREQx REG
when SELSRC = 1. When SELSRC = 0, the
FREQx REG is selected using the FSELECT pin.
0
1
0
To control the PSEL0, PSEL1, and FSELECT
bits using only one write, this command is
used. Bit D9 and Bit D10 are used to select
the PHASEx REG, and Bit 11 is used to select
the FREQx REG when SELSRC = 1. When
SELSRC = 0, the PHASEx REG is selected
using the PSEL0 and PSEL1 pins and the
FREQx REG is selected using the FSELECT pin.
0
1
Reserved. It configures the AD9832 for
test purposes.
The phase and frequency registers to be used are selected using
the FSELECT, PSEL0, and PSEL1 pins, or the corresponding
bits can be used. Bit SELSRC determines whether the bits or the
pins are used. When SELSRC = 0, the pins are used, and when
SELSRC = 1, the bits are used. When CLR is taken high,
SELSRC is set to 0 so that the pins are the default source. Data
transfers from the serial (defer) register to the 16-bit data register,
and the FSELECT and PSEL registers, occur following the 16th
falling SCLK edge.
Table 10. Controlling the AD9832
D15
D14
Command
1
0
Selects source of control for the PHASEx and
FREQx registers and enables synchronization.
Bit D13 is the SYNC bit. When this bit is high,
reading of the FSELECT, PSEL0, and PSEL1 bits/
pins and the loading of the destination register
with data is synchronized with the rising edge of
MCLK. The latency is increased by 2 MCLK cycles
when SYNC = 1. When SYNC = 0, the loading of the
data and the sampling of FSELECT/PSEL0/PSEL1
occurs asynchronously.
Bit D12 is the select source bit (SELSRC). When this
bit equals 1, the PHASEx/FREQx REG is selected
using the FSELECT, PSEL0, and PSEL1 bits. When
SELSRC = 0, the PHASEx/FREQx REG is selected
using the FSELECT, PSEL0, and PSEL1 pins.
1
SLEEP, RESET, and CLR (clear).
D13 is the SLEEP bit. When this bit equals 1, the
AD9832 is powered down, internal clocks are
disabled, and the current sources and REFOUT of
the DAC are turned off. When SLEEP = 0, the
AD9832 is powered up. When RESET (D12) = 1, the
phase accumulator is set to zero phase that
corresponds to a full-scale output. When CLR
(D11) = 1, SYNC and SELSRC are set to zero. CLR
resets to 0 automatically.
Transfer of the data from the 16-bit data register to the
destination register or from the FSELECT/PSEL register to the
respective multiplexer occurs on the next MCLK rising edge.
Because SCLK and MCLK are asynchronous, an MCLK rising
edge may occur while the data bits are in a transitional state.
This can cause a brief spurious DAC output if the register being
written to is generating the DAC output. To avoid such spurious
outputs, the AD9832 contains synchronizing circuitry.
When the SYNC bit is set to 1, the synchronizer is enabled and
data transfers from the serial register (defer register) to the 16-bit
data register, and the FSELECT/PSEL registers occur following
a two-stage pipeline delay that is triggered on the MCLK falling
edge. The pipeline delay ensures that the data is valid when the
transfer occurs. Similarly, selection of the frequency/phase
registers using the FSELECT/PSELx pins is synchronized with
the MCLK rising edge when SYNC = 1. When SYNC = 0, the
synchronizer is bypassed.
Selecting the frequency/phase registers using the pins is
synchronized with MCLK internally also when SYNC = 1 to
ensure that these inputs are valid at the MCLK rising edge. If
times t11 and t11A are met, then the inputs will be at steady state
at the MCLK rising edge. However, if times t11and t11A are
violated, the internal synchronizing circuitry will delay the
instant at which the pins are sampled, ensuring that the inputs
are valid at the sampling instant (see Figure 5).
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