參數(shù)資料
型號(hào)： EVAL-AD9832SDZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 26/28頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9832
標(biāo)準(zhǔn)包裝： 1
系列： *
Data Sheet
AD9832
Rev. E | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
FS ADJUST
AGND
IOUT
AVDD
COMP
REFIN
REFOUT
DVDD
FSELECT
PSEL1
PSEL0
DGND
MCLK
SCLK
SDATA
FSYNC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AD9832
TOP VIEW
(Not to Scale)
09090-
006
Figure 6. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
FS ADJUST
Full-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND. This determines the
magnitude of the full-scale DAC current. The relationship between RSET and the full-scale current is
IOUTFULL-SCALE = 12.5 × VREFIN/RSET, where VREFIN = 1.21 V nominal and RSET = 3.9 k typical.
2
REFIN
Voltage Reference Input. The AD9832 can be used with either the on-board reference, which is available from
the REFOUT pin, or an external reference. The reference to be used is connected to the REFIN pin. The AD9832
accepts a reference of 1.21 V nominal.
3
REFOUT
Voltage Reference Output. The AD9832 has an on-board reference of value 1.21 V nominal. The reference is
available on the REFOUT pin. This reference is used as the reference to the DAC by connecting REFOUT to REFIN.
REFOUT should be decoupled with a 10 nF capacitor to AGND.
4
DVDD
Positive Power Supply for the Digital Section. A 0.1 F decoupling capacitor should be connected between
DVDD and DGND. DVDD can have a value of 5 V ± 10% or 3.3 V ± 0%.
5
DGND
Digital Ground.
6
MCLK
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. This
clock determines the output frequency accuracy and phase noise.
7
SCLK
Serial Clock, Logic Input. Data is clocked into the AD9832 on each falling SCLK edge.
8
SDATA
Serial Data In, Logic Input. The 16-bit serial data-word is applied to this input.
9
FSYNC
Data Synchronization Signal, Logic Input. When this input goes low, the internal logic is informed that
a new word is being loaded into the device.
10
FSELECT
Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase
accumulator. The frequency register to be used can be selected using the FSELECT pin or the FSELECT bit. FSELECT
is sampled on the rising MCLK edge. FSELECT needs to be in steady state when an MCLK rising edge occurs. If
FSELECT changes value when a rising edge occurs, there is an uncertainty of one MCLK cycle as to when control is
transferred to the other frequency register. To avoid any uncertainty, a change on FSELECT should not coincide with an
MCLK rising edge. When the bit is being used to select the frequency register, the FSELECT pin should be tied to DGND.
11, 12
PSEL1,
PSEL0
Phase Select Input. The AD9832 has four phase registers. These registers can be used to alter the value being
input to the SIN ROM. The contents of the phase register are added to the phase accumulator output, the inputs
PSEL0 and PSEL1 selecting the phase register to be used. Alternatively, the phase register to be used can be
selected using the PSEL0 and PSEL1 bits. Like the FSELECT input, PSEL0 and PSEL1 are sampled on the rising
MCLK edge. Therefore, these inputs need to be in steady state when an MCLK rising edge occurs or there is an
uncertainty of one MCLK cycle as to when control is transferred to the selected phase register. When the phase
registers are being controlled by the PSEL0 and PSEL1 bits, the pins should be tied to DGND.
13
AGND
Analog Ground.
14
IOUT
Current Output. This is a high impedance current source. A load resistor should be connected between IOUT and AGND.
15
AVDD
Positive Power Supply for the Analog Section. A 0.1 F decoupling capacitor should be connected between
AVDD and AGND. AVDD can have a value of 5 V ± 10% or 3.3 V ± 10%.
16
COMP
Compensation Pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling ceramic
capacitor should be connected between COMP and AVDD.
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