參數(shù)資料
型號(hào)： EVAL-AD9837SDZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/28頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9837
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，直接數(shù)字合成（DDS）
嵌入式： 否
已用 IC / 零件： AD9837
次要屬性： 圖形用戶界面
已供物品： 板，CD，文檔
Data Sheet
AD9837
Rev. A | Page 19 of 28
APPLICATIONS INFORMATION
The various output options available from the AD9837 make
the part suitable for a wide variety of applications, including
modulation applications. The AD9837 can be used to perform
simple modulation, such as frequency shift keying (FSK). More
complex modulation schemes, such as Gaussian minimum shift
keying (GMSK) and quadrature phase shift keying (QPSK), can
also be implemented using the AD9837.
In an FSK application, the two frequency registers of the AD9837
are loaded with different values. One frequency represents the
space frequency, and the other represents the mark frequency.
Using the FSEL bit in the control register of the AD9837, the user
can modulate the carrier frequency between the two values.
The AD9837 has two phase registers, enabling the part to per-
form phase shift keying (PSK). With PSK, the carrier frequency
is phase shifted, that is, the phase is altered by an amount that
is related to the bit stream input to the modulator.
The AD9837 is also suitable for signal generator applications.
Because the MSB of the DAC data is available at the VOUT pin,
the device can be used to generate a square wave.
With its low current consumption, the part is also suitable for
applications in which it can be used as a local oscillator.
GROUNDING AND LAYOUT
The printed circuit board that houses the AD9837 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the use
of ground planes that can be separated easily. A minimum etch
technique is generally best for ground planes because it provides
the best shielding. Digital and analog ground planes should be
joined in one place only. If the AD9837 is the only device that
requires an AGND to DGND connection, the ground planes
should be connected at the AGND and DGND pins of the
AD9837. If the AD9837 is in a system where multiple devices
require AGND to DGND connections, the connection should
be made at one point only, a star ground point that should be
established as close as possible to the AD9837.
Avoid running digital lines under the device; these lines couple
noise onto the die. The analog ground plane should be allowed
to run under the AD9837 to avoid noise coupling. The power
supply lines to the AD9837 should use as large a track as possible
to provide low impedance paths and reduce the effects of glitches
on the power supply line. Fast switching signals, such as clocks,
should be shielded with digital ground to avoid radiating noise
to other sections of the board.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other to
reduce the effects of feedthrough through the board. A micro-
strip technique is by far the best but is not always possible with
a double-sided board. In this technique, the component side of
the board is dedicated to ground planes and signals are placed
on the other side.
Good decoupling is important. The AD9837 should have supply
bypassing of 0.1 μF ceramic capacitors in parallel with 10 μF
tantalum capacitors. To achieve the best performance from the
decoupling capacitors, they should be placed as close as possible
to the device, ideally right up against the device.
INTERFACING TO MICROPROCESSORS
The AD9837 has a standard serial interface that allows the part to
interface directly with several microprocessors. The device uses
an external serial clock to write the data or control information
into the device. The serial clock can have a frequency of 40 MHz
maximum. The serial clock can be continuous, or it can idle high
or low between write operations. When data or control informa-
tion is written to the AD9837, FSYNC is taken low and is held
low until the 16 bits of data are written into the AD9837. The
FSYNC signal frames the 16 bits of information that are loaded
into the AD9837.
AD9837 to 68HC11/68L11 Interface
Figure 25 shows the serial interface between the AD9837 and
the 68HC11/68L11 microcontroller. The microcontroller is con-
figured as the master by setting the MSTR bit in the SPCR to 1.
This setting provides a serial clock on SCK; the MOSI output
drives the serial data line, SDATA. Because the microcontroller
does not have a dedicated frame sync pin, the FSYNC signal is
derived from a port line (PC7). The setup conditions for correct
operation of the interface are as follows:
SCK idles high between write operations (CPOL = 0)
Data is valid on the SCK falling edge (CPHA = 1)
When data is to be transmitted to the AD9837, the FSYNC line
(PC7) is taken low. Serial data from the 68HC11/68L11 is trans-
mitted in 8-bit bytes with only eight falling clock edges occurring
in the transmit cycle. Data is transmitted MSB first. To load data
into the AD9837, PC7 is held low after the first eight bits are
transferred, and a second serial write operation is performed to
the AD9837. Only after the second eight bits are transferred
should FSYNC be taken high again.
AD9837
FSYNC
SDATA
SCLK
68HC11/68L11
PC7
MOSI
SCK
09070-
030
Figure 25. 68HC11/68L11 to AD9837 Interface
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