參數(shù)資料
型號： EVAL-AD9837SDZ
廠商： Analog Devices Inc
文件頁數(shù)： 13/28頁
文件大小： 0K
描述： BOARD EVAL FOR AD9837
產品培訓模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標準包裝： 1
主要目的： 計時，直接數(shù)字合成（DDS）
嵌入式： 否
已用 IC / 零件： AD9837
次要屬性： 圖形用戶界面
已供物品： 板，CD，文檔
AD9837
Data Sheet
Rev. A | Page 20 of 28
AD9837 to 80C51/80L51 Interface
Figure 26 shows the serial interface between the AD9837 and
the 80C51/80L51 microcontroller. The microcontroller is oper-
ated in Mode 0 so that TxD of the 80C51/80L51 drives SCLK of
the AD9837, and RxD drives the serial data line, SDATA. The
FSYNC signal is derived from a bit programmable pin on the
port (P3.3 is shown in Figure 26).
When data is to be transmitted to the AD9837, P3.3 is taken low.
The 80C51/80L51 transmits data in 8-bit bytes with only eight
falling SCLK edges occurring in each cycle. To load the remain-
ing eight bits to the AD9837, P3.3 is held low after the first eight
bits are transmitted, and a second write operation is initiated to
transmit the second byte of data. P3.3 is taken high following
the completion of the second write operation. SCLK should idle
high between the two write operations.
The 80C51/80L51 outputs the serial data in a format that has the
LSB first. The AD9837 accepts the MSB first (the four MSBs are
the control information, the next four bits are the address, and
the eight LSBs contain the data when writing to a destination
register). Therefore, the transmit routine of the 80C51/80L51
must take this into account and rearrange the bits so that the
MSB is output first.
AD9837
FSYNC
SDATA
SCLK
80C51/80L51
P3.3
RxD
TxD
09070-
031
Figure 26. 80C51/80L51 to AD9837 Interface
AD9837 to DSP56002 Interface
Figure 27 shows the interface between the AD9837 and the
DSP56002. The DSP56002 is configured for normal mode asyn-
chronous operation with a gated internal clock (SYN = 0, GCK = 1,
SCKD = 1). The frame sync pin is generated internally (SC2 = 1),
the transfers are 16 bits wide (WL1 = 1, WL0 = 0), and the frame
sync signal frames the 16 bits (FSL = 0). The frame sync signal is
available on the SC2 pin, but it must be inverted before it is applied
to the AD9837. The interface to the DSP56000/DSP56001 is
similar to that of the DSP56002.
AD9837
FSYNC
SDATA
SCLK
DSP56002
SC2
STD
SCK
09070-
032
Figure 27. DSP56002 to AD9837 Interface
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