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參數(shù)資料
| 型號： | EVAL-AD9837SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/28頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9837 |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，直接數(shù)字合成（DDS） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9837 |
| 次要屬性： | 圖形用戶界面 |
| 已供物品： | 板，CD，文檔 |
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Data Sheet
AD9837
Rev. A | Page 13 of 28
FUNCTIONAL DESCRIPTION
SERIAL INTERFACE
The AD9837 has a standard 3-wire serial interface that is
compatible with the SPI, QSPI, MICROWIRE, and DSP
interface standards.
Data is loaded into the device as a 16-bit word under the control
of a serial clock input, SCLK. The timing diagram for this oper-
ation is given in Figure 3.
FSYNC is a level triggered input that acts as a frame synchroni-
zation and chip enable input. Data can be transferred into the
device only when FSYNC is low. To start the serial data transfer,
FSYNC should be taken low, observing the minimum FSYNC
goes low, serial data is shifted into the input shift register of the
device on the falling edges of SCLK for 16 clock pulses. FSYNC
can be taken high after the 16th falling edge of SCLK, observing
the minimum SCLK falling edge to FSYNC rising edge time, t8.
Alternatively, FSYNC can be kept low for a multiple of 16 SCLK
pulses and then brought high at the end of the data transfer. In
this way, a continuous stream of 16-bit words can be loaded
while FSYNC is held low; FSYNC goes high only after the 16th
SCLK falling edge of the last word loaded.
The SCLK can be continuous, or it can idle high or low between
write operations. In either case, it must be high when FSYNC
goes low (t11).
For an example of how to program the AD9837, see the AN-1070
Application Note on the Analog Devices, Inc., website. The
LATENCY PERIOD
A latency period is associated with each asynchronous write
operation in the AD9837. If a selected frequency or phase
register is loaded with a new word, there is a delay of seven
or eight MCLK cycles before the analog output changes. The
delay can be seven or eight cycles, depending on the position
of the MCLK rising edge when the data is loaded into the
destination register.
CONTROL REGISTER
The AD9837 contains a 16-bit control register that allows the
user to configure the operation of the AD9837. All control bits
other than the MODE bit are sampled on the internal falling
edge of MCLK.
describes the individual bits of the control register. The different
functions and the various output options of the AD9837 are
described in more detail in the following sections.
To inform the AD9837 that the contents of the control register
will be altered, Bit D15 and Bit D14 must be set to 0, as shown
Table 6. Control Register Bits
D15
D14
D13 to D0
0
Control bits
SIN
ROM
PHASE
ACCUMULATOR
(28-BIT)
(LOW POWER)
10-BIT DAC
0
MUX
1
SLEEP12
SLEEP1
RESET
MODE + OPBITEN
DIV2
OPBITEN
VOUT
1
MUX
0
DIGITAL
OUTPUT
(ENABLE)
DIVIDE
BY 2
D15
0
D14
0
D13
B28
D12
HLB
D11
FSEL
D10
PSEL
D9
0
D8
RESET
D7
SLEEP1
D6
SLEEP12
D5
OPBITEN
D4
0
D3
DIV2
D2
0
D1
MODE
D0
0
09070-
024
Figure 20. Function of Control Bits
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