I2C-COMPATIBLE I" />
參數(shù)資料
型號(hào)： EVAL-ADUC7024QSZ
廠商： Analog Devices Inc
文件頁數(shù)： 79/104頁
文件大?。?/td> 0K
描述： KIT DEV QUICK START ADUC7024
產(chǎn)品培訓(xùn)模塊： ARM7 Applications & Tools
Intro to ARM7 Core & Microconverters
設(shè)計(jì)資源： ADUC7024 Dev System Schematic/Brd Outline
7024 Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC7024
所含物品： 評(píng)估板、電源、纜線、軟件和說明文檔
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Rev. F | Page 76 of 104
I2C-COMPATIBLE INTERFACES
The ADuC7019/20/21/22/24/25/26/27/28/29 support two licensed
I2C interfaces. The I2C interfaces are both implemented as a hard-
ware master and a full slave interface. Because the two I2C inter-
faces are identical, this data sheet describes only I2C0 in detail.
Note that the two masters and one of the slaves have individual
interrupts (see the Interrupt System section).
Note that when configured as an I2C master device, the
ADuC7019/20/21/22/24/25/26/27/28/29 cannot generate a
repeated start condition.
The two GPIO pins used for data transfer, SDAx and SCLx, are
configured in a wired-AND format that allows arbitration in a
multimaster system. These pins require external pull-up resistors.
Typical pull-up values are 10 k.
The I2C bus peripheral address in the I2C bus system is pro-
grammed by the user. This ID can be modified any time a
transfer is not in progress. The user can configure the interface
to respond to four slave addresses.
The transfer sequence of an I2C system consists of a master
device initiating a transfer by generating a start condition while
the bus is idle. The master transmits the slave device address
and the direction of the data transfer during the initial address
transfer. If the master does not lose arbitration and the slave
acknowledges, the data transfer is initiated. This continues until
the master issues a stop condition and the bus becomes idle.
The I2C peripheral can be configured only as a master or slave
at any given time. The same I2C channel cannot simultaneously
support master and slave modes.
Serial Clock Generation
The I2C master in the system generates the serial clock for a
transfer. The master channel can be configured to operate in
fast mode (400 kHz) or standard mode (100 kHz).
The bit rate is defined in the I2C0DIV MMR as follows:
)
(2
)
2
(
DIVL
DIVH
+
=
UCLK
CLOCK
SERIAL
f
where:
fUCLK = clock before the clock divider.
DIVH = the high period of the clock.
DIVL = the low period of the clock.
Thus, for 100 kHz operation,
DIVH = DIVL = 0xCF
and for 400 kHz,
DIVH = 0x28, DIVL = 0x3C
The I2CxDIV registers correspond to DIVH:DIVL.
Slave Addresses
The registers I2C0ID0, I2C0ID1, I2C0ID2, and I2C0ID3 contain
the device IDs. The device compares the four I2C0IDx registers
to the address byte. To be correctly addressed, the seven MSBs of
either ID register must be identical to that of the seven MSBs of
the first received address byte. The LSB of the ID registers (the
transfer direction bit) is ignored in the process of address
recognition.
I2C Registers
The I2C peripheral interface consists of 18 MMRs, which are
discussed in this section.
Table 126. I2CxMSTA Registers
Name
Address
Default Value
Access
I2C0MSTA
0xFFFF0800
0x00
R/W
I2C1MSTA
0xFFFF0900
0x00
R/W
I2CxMSTA are status registers for the master channel.
Table 127. I2C0MSTA MMR Bit Descriptions
Bit
Access
Type
Description
7
R/W
Master transmit FIFO flush. Set by user to flush
the master Tx FIFO. Cleared automatically after
the master Tx FIFO is flushed. This bit also
flushes the slave receive FIFO.
6
R
Master busy. Set automatically if the master is
busy. Cleared automatically.
5
R
Arbitration loss. Set in multimaster mode if
another master has the bus. Cleared when the
bus becomes available.
4
R
No ACK. Set automatically if there is no
acknowledge of the address by the slave
device. Cleared automatically by reading the
I2C0MSTA register.
3
R
Master receive IRQ. Set after receiving data.
Cleared automatically by reading the I2C0MRX
register.
2
R
Master transmit IRQ. Set at the end of a
transmission. Cleared automatically by writing
to the I2C0MTX register.
1
R
Master transmit FIFO underflow. Set
automatically if the master transmit FIFO is
underflowing. Cleared automatically by
writing to the I2C0MTX register.
0
R
Master TX FIFO not full. Set automatically if the
slave transmit FIFO is not full. Cleared automati-
cally by writing twice to the I2C0STX register.
Table 128. I2CxSSTA Registers
Name
Address
Default Value
Access
I2C0SSTA
0xFFFF0804
0x01
R
I2C1SSTA
0xFFFF0904
0x01
R
I2CxSSTA are status registers for the slave channel.
相關(guān)PDF資料
PDF描述
EVAL-ADUC845QSZ KIT DEV FOR ADUC845 QUICK START
HCM15DRXS CONN EDGECARD 30POS DIP .156 SLD
EVAL-ADUC832QSZ KIT DEV FOR ADUC832 QUICK START
HBM15DRXS CONN EDGECARD 30POS DIP .156 SLD
PCX1H270MCL1GS CAP ALUM 27UF 50V 20% SMD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-ADUC7026QS 制造商:Analog Devices 功能描述:MICROCONTROLLER, PRECISION ANALOG,MULTI-CHANNEL 12-BIT ADC - Bulk 制造商:Analog Devices 功能描述:EVALUATION KIT
EVAL-ADUC7026QSP 制造商:Analog Devices 功能描述:Evaluation Board For Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU 制造商:Analog Devices 功能描述:QUICK START DEVELOPMENT SYSTEM - Bulk 制造商:Analog Devices 功能描述:EVALUATION KIT
EVAL-ADUC7026QSPZ 功能描述:KIT DEV ADUC7026/7027 QUICK PLUS RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ PLUS 套件 產(chǎn)品培訓(xùn)模塊:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色產(chǎn)品:Blackfin? BF50x Series Processors 標(biāo)準(zhǔn)包裝:1 系列:Blackfin® 類型:DSP 適用于相關(guān)產(chǎn)品:ADSP-BF548 所含物品:板，軟件，4x4 鍵盤，光學(xué)撥輪，QVGA 觸摸屏 LCD 和 40G 硬盤 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相關(guān)產(chǎn)品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA
EVAL-ADUC7026QS-U1 制造商:Analog Devices 功能描述:QUICK START DEVL SYST EVAL BOARD I.C. - Bulk
EVAL-ADUC7026QSZ 功能描述:KIT DEV FOR ADUC7026/7027 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ 套件 標(biāo)準(zhǔn)包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF)
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*