參數(shù)資料
型號(hào)： EVAL-ADUC7024QSZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 95/104頁(yè)
文件大小： 0K
描述： KIT DEV QUICK START ADUC7024
產(chǎn)品培訓(xùn)模塊： ARM7 Applications & Tools
Intro to ARM7 Core & Microconverters
設(shè)計(jì)資源： ADUC7024 Dev System Schematic/Brd Outline
7024 Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ 套件
類(lèi)型： MCU
適用于相關(guān)產(chǎn)品： ADuC7024
所含物品： 評(píng)估板、電源、纜線、軟件和說(shuō)明文檔
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Rev. F | Page 90 of 104
04955-
039
LATCH
ADuC7026/
ADuC7027
AD15:AD0
A16
EEPROM
64k × 16-BIT
A0:A15
D0:D15
CS
RAM
128k × 8-BIT
A0:A15
A16
D0:D7
CS
WE
OE
WE
OE
AE
MS0
MS1
WS
RS
Figure 82. Interfacing to External EEPROM/RAM
Table 195. XMCFG Register
Name
Address
Default Value
Access
XMCFG
0xFFFFF000
0x00
R/W
XMCFG is set to 1 to enable external memory access. This must
be set to 1 before any port pins function as external memory
access pins. The port pins must also be individually enabled via
the GPxCON MMR.
Table 196. XMxCON Registers
Name
Address
Default Value
Access
XM0CON
0xFFFFF010
0x00
R/W
XM1CON
0xFFFFF014
0x00
R/W
XM2CON
0xFFFFF018
0x00
R/W
XM3CON
0xFFFFF01C
0x00
R/W
XMxCON are the control registers for each memory region.
They allow the enabling/disabling of a memory region and
control the data bus width of the memory region.
Table 197. XMxCON MMR Bit Descriptions
Bit
Description
1
Selects data bus width. Set by user to select a 16-bit data
bus. Cleared by user to select an 8-bit data bus.
0
Enables memory region. Set by user to enable the memory
region. Cleared by user to disable the memory region.
Table 198. XMxPAR Registers
Name
Address
Default Value
Access
XM0PAR
0xFFFFF020
0x70FF
R/W
XM1PAR
0xFFFFF024
0x70FF
R/W
XM2PAR
0xFFFFF028
0x70FF
R/W
XM3PAR
0xFFFFF02C
0x70FF
R/W
XMxPAR are registers that define the protocol used for
accessing the external memory for each memory region.
Table 199. XMxPAR MMR Bit Descriptions
Bit
Description
15
Enable byte write strobe. This bit is used only for two,
8-bit memory devices sharing the same memory region.
Set by the user to gate the A0 output with the WS
output. This allows byte write capability without using
BHE and BLE signals. Cleared by user to use BHE and BLE
signals.
14:12
Number of wait states on the address latch enable STROBE.
11
Reserved.
10
Extra address hold time. Set by user to disable extra hold
time. Cleared by user to enable one clock cycle of hold
on the address in read and write.
9
Extra bus transition time on read. Set by user to disable
extra bus transition time. Cleared by user to enable one
extra clock before and after the read strobe (RS).
8
Extra bus transition time on write. Set by user to disable
extra bus transition time. Cleared by user to enable one
extra clock before and after the write strobe (WS).
7:4
Number of write wait states. Select the number of wait
states added to the length of the WS pulse. 0x0 is 1 clock;
0xF is 16 clock cycles (default value).
3:0
Number of read wait states. Select the number of wait
states added to the length of the RS pulse. 0x0 is 1 clock;
0xF is 16 clock cycles (default value).
for a read cycle, a read cycle with address hold and bus turn
cycles, a write cycle with address and write hold cycles, and a
write cycle with wait sates, respectively.
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