參數(shù)資料
型號： EVAL-ADUC7128QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 26/92頁
文件大小： 0K
描述： KIT DEV FOR ADUC7128
產(chǎn)品培訓模塊： ARM7 Applications & Tools
Intro to ARM7 Core & Microconverters
設計資源： ADUC7128 Dev System Schematic
ADUC7128 Gerber Files
標準包裝： 1
系列： QuickStart™ PLUS 套件
類型： MCU
適用于相關產(chǎn)品： ADuC7128
所含物品： 評估板、電源、纜線、軟件、仿真器和說明文檔
產(chǎn)品目錄頁面： 739 (CN2011-ZH PDF)
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ADuC7128/ADuC7129
Rev. 0 | Page 32 of 92
ADC CIRCUIT OVERVIEW
The analog-to-digital converter (ADC) incorporates a fast,
multichannel, 12-bit ADC. It can operate from 3.0 V to 3.6 V
supplies and is capable of providing a throughput of up to 1 MSPS
when the clock source is 41.78 MHz. This block provides the
user with a multichannel multiplexer, differential track-and-
hold, on-chip reference, and ADC.
The ADC consists of a 12-bit successive approximation converter
based around two capacitor DACs. Depending on the input
signal configuration, the ADC can operate in one of the
following three modes:
Fully differential mode, for small and balanced signals
Single-ended mode, for any single-ended signals
Pseudo differential mode, for any single-ended signals,
taking advantage of the common mode rejection offered by
the pseudo differential input
The converter accepts an analog input range of 0 to VREF when
operating in single-ended mode or pseudo differential mode. In
fully differential mode, the input signal must be balanced around
a common-mode voltage VCM, in the range 0 V to AVDD and
with a maximum amplitude of 2 VREF (see Figure 32).
AVDD
VCM
0
2VREF
0
60
20
-02
8
Figure 32. Examples of Balanced Signals for Fully Differential Mode
A high precision, low drift, and factory-calibrated 2.5 V reference
is provided on-chip. An external reference can also be connected
as described in the Band Gap Reference section.
Single or continuous conversion modes can be initiated in software.
An external CONVST pin, an output generated from the on-chip
PLA, a Timer0, or a Timer1 overflow can also be used to
generate a repetitive trigger for ADC conversions.
If the signal has not been deasserted by the time the ADC
conversion is complete, a second conversion begins auto-
matically.
A voltage output from an on-chip band gap reference propor-
tional to absolute temperature can also be routed through the
front-end ADC multiplexer, effectively an additional ADC
channel input. This facilitates an internal temperature sensor
channel, measuring die temperature to an accuracy of ±3°C.
ADC TRANSFER FUNCTION
Pseudo Differential Mode and Single-Ended Mode
In pseudo differential or single-ended mode, the input range is
0 to VREF. The output coding is straight binary in pseudo
differential and single-ended modes with
1 LSB = FS/4096 or
2.5 V/4096 = 0.61 mV or
610 μV when VREF = 2.5 V
The ideal code transitions occur midway between successive
integer LSB values (that is, 1/2 LSB, 3/2 LSBs, 5/2 LSBs, …,
FS – 3/2 LSBs). The ideal input/output transfer characteristic is
shown in Figure 33.
O
U
T
P
UT
CO
DE
VOLTAGE INPUT
1111 1111 1111
1111 1111 1110
1111 1111 1101
1111 1111 1100
0000 0000 0011
1LSB
0V
+FS – 1LSB
0000 0000 0010
0000 0000 0001
0000 0000 0000
1LSB =
FS
4096
06
02
0-
0
29
Figure 33. ADC Transfer Function in Pseudo Differential Mode or
Single-Ended Mode
Fully Differential Mode
The amplitude of the differential signal is the difference
between the signals applied to the VIN+ and VIN pins (that is,
VIN+ VIN). The maximum amplitude of the differential signal
is, therefore, VREF to +VREF p-p (2 × VREF). This is regardless of
the common mode (CM). The common mode is the average of
the two signals (VIN+ + VIN)/2, and is, therefore, the voltage upon
which the two inputs are centered. This results in the span of
each input being CM ± VREF/2. This voltage has to be set up exter-
nally, and its range varies with VREF (see the Driving the Analog
Inputs section).
The output coding is twos complement in fully differential
mode with 1 LSB = 2 VREF/4096 or 2 × 2.5 V/4096 = 1.22 mV
when VREF = 2.5 V. The output result is ±11 bits, but this is
shifted by one to the right. This allows the result in ADCDAT to
be declared as a signed integer when writing C code. The
designed code transitions occur midway between successive
integer LSB values (that is, 1/2 LSB, 3/2 LSBs, 5/2 LSBs, …,
FS 3/2 LSBs). The ideal input/output transfer characteristic is
shown in Figure 34.
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相關代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-ADUC7128QSPZ2 制造商:AD 制造商全稱:Analog Devices 功能描述:Precision Analog Microcontroller ARM7TDMI MCU with 12-Bit ADC and DDS DAC
EVAL-ADUC7129QSPZ 制造商:Analog Devices 功能描述:- Bulk
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EVAL-ADUC812QSP 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter㈢, Multichannel 12-Bit ADC with Embedded Flash MCU
EVAL-ADUC812QSZ 功能描述:BOARD EVALUATION FOR ADUC812 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ 套件 標準包裝:1 系列:PICDEM™ 類型:MCU 適用于相關產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF)
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