參數(shù)資料
型號： EVAL-ADUC7128QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 8/92頁
文件大?。?/td> 0K
描述： KIT DEV FOR ADUC7128
產(chǎn)品培訓(xùn)模塊： ARM7 Applications & Tools
Intro to ARM7 Core & Microconverters
設(shè)計資源： ADUC7128 Dev System Schematic
ADUC7128 Gerber Files
標準包裝： 1
系列： QuickStart™ PLUS 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC7128
所含物品： 評估板、電源、纜線、軟件、仿真器和說明文檔
產(chǎn)品目錄頁面： 739 (CN2011-ZH PDF)
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ADuC7128/ADuC7129
Rev. 0 | Page 16 of 92
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
TC
K
TD
O
IOGN
D
IOV
DD
LV
DD
DG
ND
P
3.0
/P
WM
1
P
3.1
/P
WM
2
P
3.2
/P
WM
3
P
3.3
/P
WM
4
P
0.3
/A
D
C
BU
S
Y
/TR
S
T
RS
T
P
3.4
/P
WM
5
P
3.5
/P
WM
6
P
0.
4/
IRQ
0/
CO
NV
S
T
P
0.5
/IR
Q1
/A
D
C
BU
S
Y
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
ADC4
ADC3/
C
M
P
1
ADC2/
C
M
P
0
ADC1
ADC0
DACV
DD
AV
DD
AG
ND
DACG
ND
V
RE
F
P4
.5
P4
.4
P
4.3
/P
WM
TRI
P
P4
.2
P
1.0
/S
P
M
0
P
1.1
/S
P
M
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ADC5
VDACOUT
ADC9
ADC10
GNDREF
ADCNEG
AVDD
ADC12/LD1TX
ADC13/LD2TX
AGND
TMS
TDI
P4.6/SPM10
P4.7/SPM11
P0.0/BM/CMPOUT
P0.6/T1/MRST
P1.2/SPM2
P1.3/SPM3
P1.4/SPM4
P1.5/SPM5
P4.1/S2
P4.0/S1
IOVDD
IOGND
P1.6/SPM6
P1.7/SPM7
DGND
PVDD
XCLKI
XCLKO
P0.7/SPM8/ECLK/XCLK
P2.0/SPM9
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
ADuC7128
TOP VIEW
(Not to Scale)
0
60
20
-0
63
Figure 10. ADuC7128 Pin Configuration
Table 10. ADuC7128 Pin Function Descriptions
Pin
No.
Mnemonic
Type1
Description
1
ADC5
I
Single-Ended or Differential Analog Input 5/Line Driver Input.
2
VDACOUT
O
Output from DAC Buffer.
3
ADC9
I
Single-Ended or Differential Analog Input 9.
4
ADC10
I
Single-Ended or Differential Analog Input 10.
5
GNDREF
S
Ground Voltage Reference for the ADC. For optimal performance, the analog power supply
should be separated from IOGND and DGND.
6
ADCNEG
I
Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be
connected to the ground of the signal to convert. This bias point must be between
0 V and 1 V.
7, 58
AVDD
S
Analog Power.
8
ADC12/LD1TX
I/O
Single-Ended or Differential Analog Input 12/DAC Differential Negative Output.
9
ADC13/LD2TX
I/O
Single-Ended or Differential Analog Input 13/DAC Differential Positive Output.
10, 57
AGND
S
Analog Ground. Ground reference point for the analog circuitry.
11
TMS
I
JTAG Test Port Input, Test Mode Select. Debug and download access.
12
TDI
I
JTAG Test Port Input, Test Data In. Debug and download access.
13
P4.6/SPM10
I/O
General-Purpose Input and Output Port 4.6/Serial Port Mux Pin 10.
14
P4.7/SPM11
I/O
General-Purpose Input and Output Port 4.7/Serial Port Mux Pin 11.
15
P0.0/BM/CMPOUT
I/O
General-Purpose Input and Output Port 0.0/Boot Mode. The ADuC7128 enters download
mode if BM is low at reset and executes code if BM is pulled high at reset through a 1 kΩ
resistor/voltage comparator output.
16
P0.6/T1/MRST
O
General-Purpose Output Port 0.6/Timer1 Input/Power-On Reset Output.
17
TCK
I
JTAG Test Port Input, Test Clock. Debug and download access.
18
TDO
O
JTAG Test Port Output, Test Data Out. Debug and download access.
19, 41
IOGND
S
Ground for GPIO. Typically connected to DGND.
20, 42
IOVDD
S
3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.
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