參數(shù)資料
型號(hào): EVAL-ADUC7128QSPZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 69/92頁(yè)
文件大小: 0K
描述: KIT DEV FOR ADUC7128
產(chǎn)品培訓(xùn)模塊: ARM7 Applications & Tools
Intro to ARM7 Core & Microconverters
設(shè)計(jì)資源: ADUC7128 Dev System Schematic
ADUC7128 Gerber Files
標(biāo)準(zhǔn)包裝: 1
系列: QuickStart™ PLUS 套件
類型: MCU
適用于相關(guān)產(chǎn)品: ADuC7128
所含物品: 評(píng)估板、電源、纜線、軟件、仿真器和說明文檔
產(chǎn)品目錄頁(yè)面: 739 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: ADUC7128BSTZ126-RLDKR-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP
ADUC7128BCPZ126-RLDKR-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP
ADUC7128BSTZ126-RLCT-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP
ADUC7128BCPZ126-RLCT-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP
ADUC7128BSTZ126-RLTR-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP
ADUC7128BCPZ126-RLTR-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP
ADUC7128BSTZ126-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP
ADUC7128BCPZ126-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP
Rev. 0 | Page 71 of 92
Table 99. PLACLK MMR Bit Designations
Bit
Value
Description
7
Reserved.
Block 1 Clock Source Selection.
000
GPIO Clock on P0.5.
001
GPIO Clock on P0.0.
010
GPIO Clock on P0.7.
011
HCLK.
100
OCLK.
101
Timer1 Overflow.
110
Timer4 Overflow.
6:4
Other
Reserved.
3
Reserved.
Block 0 Clock Source Selection.
000
GPIO Clock on P0.5.
001
GPIO Clock on P0.0.
010
GPIO Clock on P0.7.
011
HCLK.
100
OCLK.
101
Timer1 Overflow.
110
Timer4 Overflow.
2:0
Other
Reserved.
Table 100. PLAIRQ MMR Bit Designations
Bit
Value
Description
15:13
Reserved.
12
PLA IRQ1 Enable Bit
Set by user to enable IRQ1 output from PLA
Cleared by user to disable IRQ1 output
from PLA
11:8
PLA IRQ1 Source.
0000
PLA Element 0.
0001
PLA Element 1.
1111
PLA Element 15.
7:5
Reserved.
4
PLA IRQ0 Enable Bit.
Set by user to enable IRQ0 output from PLA.
Cleared by user to disable IRQ0 output
from PLA.
3:0
PLA IRQ0 Source.
0000
PLA Element 0.
0001
PLA Element 1.
1111
PLA Element 15.
Table 101. PLAADC MMR Bit Designations
Bit
Value
Description
31:5
Reserved.
4
ADC Start Conversion Enable Bit.
Set by user to enable ADC start conversion
from PLA.
Cleared by user to disable ADC start
conversion from PLA.
3:0
ADC Start Conversion Source.
0000
PLA Element 0.
0001
PLA Element 1.
1111
PLA Element 15.
Table 102. PLADIN MMR Bit Designations
Bit
Description
31:16
Reserved.
15:0
Input Bit from Element 15 to Element 0.
Table 103. PLAOUT MMR Bit Designations
Bit
Description
31:16
Reserved.
15:0
Output Bit from Element 15 to Element 0.
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