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| 型號(hào)： | EVAL-ADUC7128QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 82/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV FOR ADUC7128 |
| 產(chǎn)品培訓(xùn)模塊： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters |
| 設(shè)計(jì)資源： | ADUC7128 Dev System Schematic ADUC7128 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC7128 |
| 所含物品： | 評(píng)估板、電源、纜線、軟件、仿真器和說明文檔 |
| 產(chǎn)品目錄頁面： | 739 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | ADUC7128BSTZ126-RLDKR-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-RLDKR-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP ADUC7128BSTZ126-RLCT-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-RLCT-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP ADUC7128BSTZ126-RLTR-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-RLTR-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP ADUC7128BSTZ126-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP |
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ADuC7128/ADuC7129
Rev. 0 | Page 83 of 92
EXTERNAL MEMORY INTERFACING
The ADuC7129 is the only model in the series that features an
external memory interface. The external memory interface requires
a larger number of pins. This is why it is only available on larger
pin count packages. The XMCFG MMR must be set to 1 to use
the external port.
Although 32-bit addresses are supported internally, only the lower
16 bits of the address are on external pins.
The memory interface can address up to four 128 kB regions of
asynchronous memory (SRAM and/or EEPROM).
The pins required for interfacing to an external memory are
shown in Table 118.
Table 118. External Memory Interfacing Pins
Pin
Function
AD[15:0]
Address/Data Bus.
A16
Extended Addressing for 8-Bit Memory Only.
MS[3:0]
Memory Select.
WR (WR)
Write Strobe.
RS (RS)
Read Strobe.
AE
Address Latch Enable.
BHE, BLE
Byte Write Capability.
There are four external memory regions available, as described
in Table 119. Associated with each region are the MS[3:0] pins.
These signals allow access to the particular region of external
memory. The size of each memory region can be 128 kB
maximum, 64 k × 16, or 128 k × 8. To access 128 kB with an
8-bit memory, an extra address line (A16) is provided. (See the
example in Figure 61). The four regions are configured inde-
pendently.
Table 119. Memory Regions
Address Start
Address End
Contents
0x10000000
0x1000FFFF
External Memory 0
0x20000000
0x2000FFFF
External Memory 1
0x30000000
0x3000FFFF
External Memory 2
0x40000000
0x4000FFFF
External Memory 3
Each external memory region can be controlled through three
MMRs: XMCFG, XMxCON, and XMxPAR.
06
02
0-
0
68
LATCH
ADuC7128/
ADuC7129
AD15:0
A16
EPROM
64k × 16-BIT
A0:15
D0 TO D15
CS
RAM
128k × 8-BIT
A0:15
A16
D0 TO D7
CS
WE
OE
WE
OE
AE
MS0
MS1
WS
RS
Figure 61. Interfacing to External EPROM/RAM
XMCFG Register
Name
Address
Default Value
Access
XMCFG
0xFFFFF000
0x00
R/W
XMCFG is set to 1 to enable external memory access. This must
be set to 1 before any port pins function as external memory
access pins. The port pins must also be individually enabled via
the GPxCON MMR.
XMxCON Registers
Name
Address
Default Value
Access
XM0CON
0xFFFFF010
0x00
R/W
XM1CON
0xFFFFF014
0x00
R/W
XM2CON
0xFFFFF018
0x00
R/W
XM3CON
0xFFFFF01C
0x00
R/W
XMxCON registers are the control registers for each memory
region. They allow the enabling/disabling of a memory region
and control the data bus width of the memory region.
Table 120. XMxCON MMR Bit Designations
Bit
Description
1
Data Bus Width Select.
Set by the user to select a 16-bit data bus.
Cleared by the user to select an 8-bit data bus.
0
Memory Region Enable.
Set by the user to enable memory region.
Cleared by the user to disable the memory region.
XMxPAR Registers
Name
Address
Default Value
Access
XM0PAR
0xFFFFF020
0x70FF
R/W
XM1PAR
0xFFFFF024
0x70FF
R/W
XM2PAR
0xFFFFF028
0x70FF
R/W
XM3PAR
0xFFFFF02C
0x70FF
R/W
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