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參數(shù)資料
| 型號： | EVAL-ADUC7128QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 87/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV FOR ADUC7128 |
| 產(chǎn)品培訓模塊： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters |
| 設計資源： | ADUC7128 Dev System Schematic ADUC7128 Gerber Files |
| 標準包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關產(chǎn)品： | ADuC7128 |
| 所含物品： | 評估板、電源、纜線、軟件、仿真器和說明文檔 |
| 產(chǎn)品目錄頁面： | 739 (CN2011-ZH PDF) |
| 相關產(chǎn)品： | ADUC7128BSTZ126-RLDKR-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-RLDKR-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP ADUC7128BSTZ126-RLCT-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-RLCT-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP ADUC7128BSTZ126-RLTR-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-RLTR-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP ADUC7128BSTZ126-ND - IC DAS MCU ARM7 ADC/DDS 64-LQFP ADUC7128BCPZ126-ND - IC DAS MCU ARM7 ADC/DDS 64-LFCSP |
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ADuC7128/ADuC7129
Rev. 0 | Page 88 of 92
In these cases, tie the AGND pins and IOGND pins of the
ADuC7128/ADuC7129 to the analog ground plane, as shown
in Figure 69b. In systems with only one ground plane, ensure
that the digital and analog components are physically separated
onto separate halves of the board such that digital return currents
do not flow near analog circuitry and vice versa. The ADuC7128/
ADuC7129 can then be placed between the digital and analog
sections, as illustrated in Figure 69c.
a.
PLACE ANALOG
COMPONENTS HERE
PLACE DIGITAL
COMPONENTS HERE
AGND
DGND
b.
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS HERE
AGND
DGND
c.
PLACE ANALOG
COMPONENTS HERE
PLACE DIGITAL
COMPONENTS HERE
GND
06
02
0-
0
59
Figure 69. System Grounding Schemes
In all of these scenarios, and in more complicated real-life
applications, keep in mind the flow of current from the supplies
and back to ground. Make sure the return paths for all currents
are as close as possible to the paths the currents took to reach
their destinations. For example, do not power components on
force return currents from IOVDD to flow through AGND.
Avoid digital currents from flowing under analog circuitry,
which could happen if the user places a noisy digital chip on the
left half of the board (see Figure 69c). Whenever possible, avoid
large discontinuities in the ground planes (such as are formed
by a long trace on the same layer) because they force return
signals to travel a longer path. Make all connections to the ground
plane directly, with little or no trace separating the pin from its
via to ground.
If a user plans to connect fast logic signals (rise/fall time < 5 ns)
to any of the digital inputs of the ADuC7128/ADuC7129, add
a series resistor to each relevant line to keep rise and fall times
longer than 5 ns at the ADuC7128/ADuC7129 input pins.
A value of 100 Ω or 200 Ω is usually sufficient to prevent high
speed signals from coupling capacitively into the ADuC7128/
ADuC7129 and affecting the accuracy of ADC conversions.
CLOCK OSCILLATOR
The clock source for the ADuC7128/ADuC7129 can be gener-
ated by the internal PLL or by an external clock input. To use
the internal PLL, connect a 32.768 kHz parallel resonant crystal
between XCLKI and XCLKO as shown Figure 70. External
capacitors should be connected as per the crystal manufacturer’s
recommendations. Note that the crystal pads already have an
internal capacitance of typically 10 pF. Users should ensure that
the total capacitance (10 pF internal + external capacitance)
does not exceed the manufacturer rating.
The 32 kHz crystal allows the PLL to lock correctly to give a
frequency of 41.78 MHz. If no external crystal is present, the
internal oscillator is used to give a frequency of 41.78 MHz ±
3% typically.
ADuC7128
TO
INTERNAL
PLL
12pF
XCLKI
32.768kHz
12pF
XCLKO
06
02
0-
06
0
Figure 70. External Parallel Resonant Crystal Connections
To use an external source clock input instead of the PLL, Bit 1
and Bit 0 of PLLCON must be modified. The external clock
uses the XCLK pin.
ADuC7128
TO
FREQUENCY
DIVIDER
XCLKI
XCLK
EXTERNAL
CLOCK
SOURCE
06
02
0
-06
1
Figure 71. Connecting an External Clock Source
Whether using the internal PLL or an external clock source, the
specified operational clock speed range of the ADuC7128/
ADuC7129 is 50 kHz to 41.78 MHz to ensure correct operation
of the analog peripherals and Flash/EE.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADUC7128QSPZ2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Precision Analog Microcontroller ARM7TDMI MCU with 12-Bit ADC and DDS DAC |
| EVAL-ADUC7129QSPZ | 制造商:Analog Devices 功能描述:- Bulk |
| EVAL-ADUC812QS | 制造商:Analog Devices 功能描述:DEVELOPMENT KIT SYSTEM |
| EVAL-ADUC812QSP | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter㈢, Multichannel 12-Bit ADC with Embedded Flash MCU |
| EVAL-ADUC812QSZ | 功能描述:BOARD EVALUATION FOR ADUC812 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ 套件 標準包裝:1 系列:PICDEM™ 類型:MCU 適用于相關產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF) |
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