參數(shù)資料
型號(hào)： EVAL-ADUC842QSPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 18/88頁(yè)
文件大小： 0K
描述： KIT DEV QUICK START ADUC842
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
類(lèi)型： MCU
適用于相關(guān)產(chǎn)品： ADuC842
所含物品： 評(píng)估板、電源、纜線、軟件、仿真器和說(shuō)明文檔
ADuC841/ADuC842/ADuC843
Rev. 0 | Page 25 of 88
ADCCON2—(ADC Control SFR 2)
The ADCCON2 register controls ADC channel selection and
conversion modes as detailed below.
SFR Address
D8H
SFR Power-On Default
00H
Bit Addressable
Yes
Table 8. ADCCON2 SFR Bit Designations
Bit No.
Name
Description
7
ADCI
ADC Interrupt Bit.
Set by hardware at the end of a single ADC conversion cycle or at the end of a DMA block conversion.
Cleared by hardware when the PC vectors to the ADC interrupt service routine. Otherwise, the ADCI bit is cleared
by user code.
6
DMA
DMA Mode Enable Bit.
Set by the user to enable a preconfigured ADC DMA mode operation. A more detailed description of this mode is
given in the ADC DMA Mode section. The DMA bit is automatically set to 0 at the end of a DMA cycle. Setting this
bit causes the ALE output to cease; it will start again when DMA is started and will operate correctly after DMA is
complete.
5
CCONV
Continuous Conversion Bit.
Set by the user to initiate the ADC into a continuous mode of conversion. In this mode, the ADC starts converting
based on the timing and channel configuration already set up in the ADCCON SFRs; the ADC automatically starts
another conversion once a previous conversion has completed.
4
SCONV
Single Conversion Bit.
Set to initiate a single conversion cycle. The SCONV bit is automatically reset to 0 on completion of the single
conversion cycle.
3
2
1
0
CS3
CS2
CS1
CS0
Channel Selection Bits.
Allow the user to program the ADC channel selection under software control. When a conversion is initiated, the
converted channel is the one pointed to by these channel selection bits. In DMA mode, the channel selection is
derived from the channel ID written to the external memory.
CS3
0
1
CS2
0
1
0
1
CS1
0
1
0
1
0
1
0
1
CS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CH#
0
1
2
3
4
5
6
7
Temp Monitor
DAC0
DAC1
AGND
VREF
DMA STOP
Requires minimum of 1 s to acquire.
Only use with internal DAC output buffer on.
Place in XRAM location to finish DMA sequence; refer to
the ADC DMA Mode section.
All other combinations reserved.
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