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| 型號： | EVAL-ADUC842QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV QUICK START ADUC842 |
| 標準包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC842 |
| 所含物品： | 評估板、電源、纜線、軟件、仿真器和說明文檔 |
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ADuC841/ADuC842/ADuC843
Rev. 0 | Page 29 of 88
If using the temperature sensor as the ADC input, the ADC
should be configured to use an ADCCLK of MCLK/32 and four
acquisition clocks.
Increasing the conversion time on the temperature monitor
channel improves the accuracy of the reading. To further
improve the accuracy, an external reference with low tempera-
ture drift should also be used.
ADC DMA Mode
The on-chip ADC has been designed to run at a maximum
conversion speed of 2.38 s (420 kHz sampling rate). When
converting at this rate, the ADuC841/ADuC842/ADuC843
MicroConverter has 2 s to read the ADC result and to store the
result in memory for further postprocessing; otherwise the next
ADC sample could be lost. In an interrupt driven routine, the
MicroConverter would also have to jump to the ADC interrupt
service routine, which also increases the time required to store
the ADC results. In applications where the parts cannot sustain
the interrupt rate, an ADC DMA mode is provided.
To enable DMA mode, Bit 6 in ADCCON2 (DMA) must be set,
which allows the ADC results to be written directly to a 16 MByte
external static memory SRAM (mapped into data memory
space) without any interaction from the core of the part. This
mode allows the part to capture a contiguous sample stream at
full ADC update rates (420 kHz).
Typical DMA Mode Configuration Example
Setting the parts to DMA mode consists of the following steps:
1.
The ADC must be powered down. This is done by ensuring
that MD1 and MD0 are both set to 0 in ADCCON1.
2.
The DMA address pointer must be set to the start address
of where the ADC results are to be written. This is done by
writing to the DMA mode address pointers DMAL, DMAH,
and DMAP. DMAL must be written to first, followed by
DMAH, and then by DMAP.
3.
The external memory must be preconfigured. This consists
of writing the required ADC channel IDs into the top four
bits of every second memory location in the external
SRAM, starting at the first address specified by the DMA
address pointer. Because the ADC DMA mode operates
independently from the ADuC841/ADuC842/ADuC843
core, it is necessary to provide it with a stop command.
This is done by duplicating the last channel ID to be
converted followed by 1111 into the next channel selection
field. A typical preconfiguration of external memory is
shown in Figure 34.
11
1
00
1
00
1
10
0
01
0
1
00
1
0
00000AH
000000H
CONVERT ADC CH 2
CONVERT ADC CH 5
CONVERT ADC CH 3
CONVERT TEMP SENSOR
STOP COMMAND
REPEAT LAST CHANNEL
FOR A VALID STOP
CONDITION
03260-
0-
033
Figure 34. Typical DMA External Memory Preconfiguration
4.
The DMA is initiated by writing to the ADC SFRs in the
following sequence:
a.
ADCCON2 is written to enable the DMA mode, i.e.,
MOV ADCCON2, #40H; DMA mode enabled.
b.
ADCCON1 is written to configure the conversion
time and power-up of the ADC. It can also enable
Timer 2 driven conversions or external triggered
conversions if required.
c.
ADC conversions are initiated. This is done by starting
single conversions, starting Timer 2, running for
Timer 2 conversions, or receiving an external trigger.
When the DMA conversions are complete, the ADC interrupt
bit, ADCI, is set by hardware, and the external SRAM contains
the new ADC conversion results as shown in Figure 35. Note
that no result is written to the last two memory locations.
When the DMA mode logic is active, it takes the responsibility
of storing the ADC results away from both the user and the core
logic of the part. As the DMA interface writes the results of the
ADC conversions to external memory, it takes over the external
memory interface from the core. Thus, any core instructions
that access the external memory while DMA mode is enabled
does not get access to the external memory. The core executes
the instructions, and they take the same time to execute, but
they cannot access the external memory.
11
00
11
00
11
10
0
01
0
1
00
10
00000A H
000000H
CONVERSION RESULT
FOR ADC CH 2
CONVERSION RESULT
FOR ADC CH 5
CONVERSION RESULT
FOR ADC CH 3
CONVERSION RESULT
FOR TEMP SENSOR
STOP COMMAND
NO CONVERSION
RESULT WRITTEN HERE
03260-
0-
034
Figure 35. Typical External Memory Configuration Post ADC DMA Operation
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