參數(shù)資料
型號(hào)： EVAL-ADUC842QSPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 62/88頁(yè)
文件大?。?/td> 0K
描述： KIT DEV QUICK START ADUC842
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC842
所含物品： 評(píng)估板、電源、纜線、軟件、仿真器和說(shuō)明文檔
ADuC841/ADuC842/ADuC843
Rev. 0 | Page 65 of 88
UART SERIAL INTERFACE
The serial port is full-duplex, meaning it can transmit and
receive simultaneously. It is also receive-buffered, meaning it
can begin receiving a second byte before a previously received
byte has been read from the receive register. However, if the first
byte still has not been read by the time reception of the second
byte is complete, the first byte is lost. The physical interface to
the serial data network is via Pins RxD(P3.0) and TxD(P3.1),
while the SFR interface to the UART is comprised of SBUF and
SCON, as described below.
SBUF
Both the serial port receive and transmit registers are accessed
through the SBUF SFR (SFR address = 99H). Writing to SBUF
loads the transmit register, and reading SBUF accesses a
physically separate receive register.
SCON UART
Serial Port Control Register
SFR Address
98H
Power-On Default
00H
Bit Addressable
Yes
Table 32. SCON SFR Bit Designations
Bit No.
Name
Description
7
SM0
UART Serial Mode Select Bits.
These bits select the serial port operating mode as follows:
SM0
SM1
Selected Operating Mode.
0
Mode 0: Shift Register, fixed baud rate (Core_Clk/2).
0
1
Mode 1: 8-bit UART, variable baud rate.
1
0
Mode 2: 9-bit UART, fixed baud rate (Core_Clk/32) or (Core_Clk/16).
6
SM1
1
Mode 3: 9-bit UART, variable baud rate.
5
SM2
Multiprocessor Communication Enable Bit.
Enables multiprocessor communication in Modes 2 and 3.
In Mode 0, SM2 must be cleared.
In Mode 1, if SM2 is set, RI is not activated if a valid stop bit was not received. If SM2 is cleared, RI is set as soon as the
byte of data has been received.
In Modes 2 or 3, if SM2 is set, RI is not activated if the received 9th data bit in RB8 is 0.
If SM2 is cleared, RI is set as soon as the byte of data has been received.
4
REN
Serial Port Receive Enable Bit.
Set by user software to enable serial port reception.
Cleared by user software to disable serial port reception.
3
TB8
Serial Port Transmit (Bit 9).
The data loaded into TB8 is the 9th data bit transmitted in Modes 2 and 3.
2
RB8
Serial Port Receiver Bit 9.
The 9th data bit received in Modes 2 and 3 is latched into RB8. For Mode 1, the stop bit is latched into RB8.
1
TI
Serial Port Transmit Interrupt Flag.
Set by hardware at the end of the 8th bit in Mode 0, or at the beginning of the stop bit in Modes 1, 2, and 3.
TI must be cleared by user software.
0
RI
Serial Port Receive Interrupt Flag.
Set by hardware at the end of the 8th bit in Mode 0, or halfway through the stop bit in Modes 1, 2, and 3.
RI must be cleared by software.
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