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| 型號(hào)： | EVAL-ADUC842QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 47/88頁(yè) |
| 文件大小： | 0K |
| 描述： | KIT DEV QUICK START ADUC842 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC842 |
| 所含物品： | 評(píng)估板、電源、纜線、軟件、仿真器和說(shuō)明文檔 |
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ADuC841/ADuC842/ADuC843
Rev. 0 | Page 51 of 88
DUAL DATA POINTER
The ADuC841/ADuC842/ADuC843 incorporate two data
pointers. The second data pointer is a shadow data pointer and
is selected via the data pointer control SFR (DPCON). DPCON
also includes some useful features such as automatic hardware
post-increment and post-decrement as well as automatic data
pointer toggle. DPCON is described in Table 21.
DPCON
Data Pointer Control SFR
SFR Address
A7H
Power-On Default
00H
Bit Addressable
No
Table 21. DPCON SFR Bit Designations
Bit No.
Name
Description
7
----
Reserved.
6
DPT
Data Pointer Automatic Toggle Enable.
Cleared by the user to disable autoswapping of the DPTR.
Set in user software to enable automatic toggling of the DPTR after each each MOVX or MOVC instruction.
5
DP1m1
Shadow Data Pointer Mode.
These two bits enable extra modes of the shadow data pointer’s operation, allowing for more compact and more
efficient code size and execution.
m1
m0
Behavior of the shadow data pointer.
0
8052 behavior.
0
1
DPTR is post-incremented after a MOVX or a MOVC instruction.
1
0
DPTR is post-decremented after a MOVX or MOVC instruction.
4
DP1m0
1
DPTR LSB is toggled after a MOVX or MOVC instruction. (This instruction can be useful for moving
8-bit blocks to/from 16-bit devices.)
3
DP0m1
Main Data Pointer Mode.
These two bits enable extra modes of the main data pointer operation, allowing for more compact and more efficient
code size and execution.
m1
m0
Behavior of the main data pointer.
0
8052 behavior.
0
1
DPTR is post-incremented after a MOVX or a MOVC instruction.
1
0
DPTR is post-decremented after a MOVX or MOVC instruction.
1
DPTR LSB is toggled after a MOVX or MOVC instruction.
2
DP0m0
(This instruction can be useful for moving 8-bit blocks to/from 16-bit devices.)
1
----
This bit is not implemented to allow the INC DPCON instruction toggle the data pointer without incrementing the rest
of the SFR.
0
DPSEL
Data Pointer Select.
Cleared by the user to select the main data pointer. This means that the contents of this 24-bit register are placed into
the three SFRs: DPL, DPH, and DPP.
Set by the user to select the shadow data pointer. This means that the contents of a separate 24-bit register appears in
the three SFRs: DPL, DPH, and DPP.
Note 1: This is the only place where the main and shadow data
pointers are distinguished. Everywhere else in this data sheet
wherever the DPTR is mentioned, operation on the active
DPTR is implied.
Note 2: Only MOVC/MOVX @DPTR instructions are relevant
above. MOVC/MOVX PC/@Ri instructions do not cause the
DPTR to automatically post increment/decrement, and so on.
To illustrate the operation of DPCON, the following code copies
256 bytes of code memory at address D000H into XRAM
starting from Address 0000H.
MOV DPTR,#0
; Main DPTR = 0
MOV DPCON,#55H
; Select shadow DPTR
; DPTR1 increment mode,
; DPTR0 increment mode
; DPTR auto toggling ON
MOV DPTR,#0D000H
; Shadow DPTR = D000H
MOVELOOP:
CLR A
MOVC A,@A+DPTR
; Get data
; Post Inc DPTR
; Swap to Main DPTR (Data)
MOVX @DPTR,A
; Put ACC in XRAM
; Increment main DPTR
; Swap Shadow DPTR (Code)
MOV A, DPL
JNZ MOVELOOP
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