參數(shù)資料
型號： EVAL-ADUC842QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 32/88頁
文件大?。?/td> 0K
描述： KIT DEV QUICK START ADUC842
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC842
所含物品： 評估板、電源、纜線、軟件、仿真器和說明文檔
ADuC841/ADuC842/ADuC843
Rev. 0 | Page 38 of 88
USER INTERFACE TO ON-CHIP PERIPHERALS
This section gives a brief overview of the various peripherals
also available on-chip. A summary of the SFRs used to control
and configure these peripherals is also given.
DAC
The ADuC841/ADuC842 incorporate two 12-bit voltage output
DACs on-chip. Each has a rail-to-rail voltage output buffer
capable of driving 10 k/100 pF. Each has two selectable ranges,
0 V to VREF (the internal band gap 2.5 V reference) and 0 V to
AVDD. Each can operate in 12-bit or 8-bit mode.
Both DACs share a control register, DACCON, and four data
registers, DAC1H/L, DAC0/L. Note that in 12-bit asynchronous
mode, the DAC voltage output is updated as soon as the DACL
data SFR has been written; therefore, the DAC data registers
should be updated as DACH first, followed by DACL. Note that
for correct DAC operation on the 0 V to VREF range, the ADC
must be switched on. This results in the DAC using the correct
reference value.
DACCON
DAC Control Register
SFR Address
FDH
Power-On Default
04H
Bit Addressable
No
Table 15. DACCON SFR Bit Designations
Bit No.
Name
Description
7
MODE
The DAC MODE bit sets the overriding operating mode for both DACs.
Set to 1 by the user to select 8-bit mode (write 8 bits to DACxL SFR).
Set to 0 by the user to select 12-bit mode.
6
RNG1
DAC1 Range Select Bit.
Set to 1 by the user to select the range for DAC1 as 0 V to VDD.
Set to 0 by the user to select the range for DAC1 as 0 V to VREF.
5
RNG0
DAC0 Range Select Bit.
Set to 1 by the user to select the range for DAC0 as 0 V to VDD.
Set to 0 by the user to select the range for DAC0 as 0 V to VREF.
4
CLR1
DAC1 Clear Bit.
Set to 1 by the user to leave the output of DAC1 at its normal level.
Set to 0 by the user to force the output of DAC1 to 0 V.
3
CLR0
DAC0 Clear Bit.
Set to 1 by the user to leave the output of DAC0 at its normal level.
Set to 0 by the user to force the output of DAC0 to 0 V.
2
SYNC
DAC0/1 Update Synchronization Bit.
When set to 1, the DAC outputs update as soon as DACxL SFRs are written. The user can simultaneously update
both DACs by first updating the DACxL/H SFRs while SYNC is 0. Both DACs then update simultaneously when the
SYNC bit is set to 1.
1
PD1
DAC1 Power-Down Bit.
Set to 1 by the user to power on DAC1.
Set to 0 by the user to power off DAC1.
0
PD0
DAC0 Power-Down Bit.
Set to 1 by the user to power on DAC0.
Set to 0 by the user to power off DAC0.
DACxH/L
DAC Data Registers
Function
DAC data registers, written by the user to update the DAC output.
SFR Address
DAC0L (DAC0 Data Low Byte) -> F9H; DAC1L (DAC1 Data Low Byte) -> FBH
DACH (DAC0 Data High Byte) -> FAH; DAC1H (DAC1 Data High Byte) -> FCH
Power-On Default
00H
All Four Registers.
Bit Addressable
No
All Four Registers.
The 12-bit DAC data should be written into DACxH/L right-justified such that DACxL contains the lower 8 bits, and the lower nibble of
DACxH contains the upper 4 bits.
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