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參數(shù)資料
| 型號(hào)： | FLEX10K |
| 廠商： | Altera Corporation |
| 英文描述： | Embedded Programmable Logic Family |
| 中文描述： | 嵌入式可編程邏輯系列 |
| 文件頁(yè)數(shù)： | 113/114頁(yè) |
| 文件大小： | 1422K |
| 代理商： | FLEX10K |
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Altera Corporation
113
FLEX 10K Embedded Programmable Logic Family Data Sheet
Notes to tables:
(1)
All pins that are not listed are user I/O pins.
(2)
Pin-out information on FLEX 10KA devices (except EPF10K50V, EPF10K130V, and EPF10K100A devices) and
FLEX 10KB devices are preliminary. Contact Altera Applications for the latest pin-out information.
(3)
This pin is a dedicated pin; it is not available as a user I/O pin.
(4)
This pin can be used as a user I/O pin if it is not used for its device-wide or configuration function.
(5)
This pin can be used as a user I/O pin after configuration.
(6)
This pin is tri-stated in user mode.
(7)
The optional JTAG pin
TRST
is not used in the 144-pin TQFP package.
(8)
To maintain pin compatibility when transferring to the EPF10K10 device from any other device in the 208-pin PQFP
package, do not use these pins as user I/O pins.
(9)
The user I/O pin count includes dedicated input pins, dedicated clock pins, and all I/O pins.
(10) To maintain pin compatibility when transferring to the EPF10K30 device from any other device in the 356-pin BGA
package, do not use these pins as user I/O pins.
(11) To maintain pin compatibility when transferring from the EPF10K100 to the EPF10K70 in the 503-pin PGA package,
do not use these pins as user I/O pins.
(12) This pin shows the status of the ClockLock and ClockBoost circuitry. When the ClockLock and ClockBoost circuitry
is locked to the incoming clock and generates an internal clock,
LOCK
is driven high.
LOCK
remains high if a periodic
clock stops clocking. The
LOCK
function is optional; if the
LOCK
output is not used, this pin is a user I/O pin.
(13) This pin drives the ClockLock and ClockBoost circuitry.
(14) To maintain pin compatibility when transferring a to the EPF10K100A device from another device in the 600-pin
BGA package, do not use these pin as user I/O pins.
(15) This pin is the power or ground for the ClockLock and ClockBoost circuitry. To ensure noise resistance, the power
and ground supply to the ClockLock and ClockBoost circuitry should be isolated from the power and ground to the
rest of the device.
No Connect (N.C.)
(14)
–
–
AK5, AL4, AM3, AM2,
AM1, AJ5, AL2, AK4,
AL1, AK3, AJ4, AH5,
AK2, AK1, AJ3, AJ2,
G1, G2, G3, F1, F2,
H5, G4, F3, E1, E3,
F4, G5, D1, D2, D3,
E4, E32, D33, D34,
D35, G31, F32, E33,
E34, E35, F33, G32,
H31, F34, G33, G34,
G35, AB34, AB33,
AB32, AB31, AC35,
AC34, AC33, AC32,
AC31, AD34, AD33,
AD32, AD31, AE35,
AE34, AE33
406
–
Total User I/O Pins
(9)
406
470
470
Table 26. FLEX 10K Pin-Outs (Part 3 of 3)
Notes (1), (2)
Pin Name
503-Pin PGA
EPF10K100
599-Pin PGA
EPF10K130V
EPF10K250A
600-Pin BGA
EPF10K100A
600-Pin BGA
EPF10K130V
EPF10K250A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FLEX10KA | Embedded Programmable Logic Family |
| FLEX10KE | Embedded Programmable Logic Family |
| FLEX6000 | Programmable Logic Device Family |
| FLEX8000 | PROGRAMMABLE LOGIC DEVICES FAMILY |
| FLL120MK | L-Band Medium & High Power GaAs FET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FLEX10K_03 | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Embedded Programmable Logic Device Family |
| FLEX10KA | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Embedded Programmable Logic Family |
| FLEX10KE | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Embedded Programmable Logic Device |
| FLEX110 | 功能描述:開發(fā)板和工具包 - PIC / DSPIC Multibus Pack RoHS:否 制造商:Microchip Technology 產(chǎn)品:Starter Kits 工具用于評(píng)估:chipKIT 核心:Uno32 接口類型: 工作電源電壓: |
| FLEX111 | 功能描述:開發(fā)板和工具包 - PIC / DSPIC Fasttrack suite RoHS:否 制造商:Microchip Technology 產(chǎn)品:Starter Kits 工具用于評(píng)估:chipKIT 核心:Uno32 接口類型: 工作電源電壓: |
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