參數(shù)資料
型號(hào): FLEX10K
廠商: Altera Corporation
英文描述: Embedded Programmable Logic Family
中文描述: 嵌入式可編程邏輯系列
文件頁數(shù): 16/114頁
文件大?。?/td> 1422K
代理商: FLEX10K
16
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Figure 7 shows how an
n
-bit full adder can be implemented in
n
+ 1 LEs
with the carry chain. One portion of the LUT generates the sum of two bits
using the input signals and the carry-in signal; the sum is routed to the
output of the LE. The register can be bypassed for simple adders, but can
be used for an accumulator function. Another portion of the LUT and the
carry chain logic generate the carry-out signal, which is routed directly to
the carry-in signal of the next-higher-order bit. The final carry-out signal
is routed to an LE, where it can be used as a general-purpose signal.
Figure 7. Carry Chain Operation (n-bit Full Adder)
LUT
a1
b1
Carry Chain
s1
LE1
Register
a2
b2
Carry Chain
s2
LE2
Register
Carry Chain
sn
LEn
Register
an
bn
Carry Chain
Carry-Out
LEn + 1
Register
Carry-In
LUT
LUT
LUT
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