參數(shù)資料
型號(hào): FLEX10K
廠商: Altera Corporation
英文描述: Embedded Programmable Logic Family
中文描述: 嵌入式可編程邏輯系列
文件頁(yè)數(shù): 18/114頁(yè)
文件大小: 1422K
代理商: FLEX10K
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18
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Figure 8. Cascade Chain Operation
LE Operating Modes
The FLEX 10K LE can operate in the following four modes:
I
I
I
I
Normal mode
Arithmetic mode
Up/down counter mode
Clearable counter mode
Each of these modes uses LE resources differently. In each mode, seven
available inputs to the LEthe four data inputs from the LAB local
interconnect, the feedback from the programmable register, and the carry-
in and cascade-in from the previous LEare directed to different
destinations to implement the desired logic function. Three inputs to the
LE provide clock, clear, and preset control for the register. The
MAX+PLUS II software, in conjunction with parameterized functions
such as LPM and DesignWare functions, automatically chooses the
appropriate mode for common functions such as counters, adders, and
multipliers. If required, the designer can also create special-purpose
functions to use an LE operating mode for optimal performance.
The architecture provides a synchronous clock enable to the register in all
four modes. The MAX+PLUS II software can set
register synchronously, providing easy implementation of fully
synchronous designs.
DATA1
to enable the
LE1
LUT
LE2
LUT
d[3..0]
d[7..4]
d[(4n-1)..(4n-4)]
d[3..0]
d[7..4]
d[(4n-1)..(4n-4)]
LEn
LE1
LE2
LEn
LUT
LUT
LUT
LUT
AND Cascade Chain
OR Cascade Chain
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