參數(shù)資料
型號: FLEX10K
廠商: Altera Corporation
英文描述: Embedded Programmable Logic Family
中文描述: 嵌入式可編程邏輯系列
文件頁數(shù): 31/114頁
文件大?。?/td> 1422K
代理商: FLEX10K
Altera Corporation
31
FLEX 10K Embedded Programmable Logic Family Data Sheet
Signals on the peripheral control bus can also drive the four global signals,
referred to as
GLOBAL0
through
GLOBAL3
in Tables 7 and 8. The internally
generated signal can drive the global signal, providing the same
low-skew, low-delay characteristics for an internally generated signal as
for a signal driven by an input. This feature is ideal for internally
generated clear or clock signals with high fan-out.
The chip-wide output enable pin is an active-low pin that can be used to
tri-state all pins on the device. This option can be set in the design file.
Additionally, the registers in the IOE can be reset by the chip-wide reset
pin.
Row-to-IOE Connections
When an IOE is used as an input signal, it can drive two separate row
channels. The signal is accessible by all LEs within that row. When an IOE
is used as an output, the signal is driven by a multiplexer that selects a
signal from the row channels. Up to eight IOEs connect to each side of
each row channel. See Figure 14.
Figure 14. FLEX 10K Row-to-IOE Connections
n
n
Each IOE is driven by an
m-to-1 multiplexer.
Each IOE can drive up to two
row channels.
IOE8
IOE1
m
m
Row FastTrack
Interconnect
n
The values for m and n are provided in Table 9.
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