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參數(shù)資料
| 型號(hào)： | FQB60N03L |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | JFETs |
| 英文描述： | N-Channel Logic Level PWM Optimized Power MOSFET |
| 中文描述： | 51 A, 30 V, 0.0135 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-263AB |
| 封裝： | TO-263AB, 3 PIN |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 238K |
| 代理商： | FQB60N03L |
2002 Fairchild Semiconductor Corporation
FQB60N03L Rev. B
F
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T
JM
, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
DM
, in an
application.
Therefore
temperature, T
A
(
o
C), and thermal resistance R
θ
JA
(
o
C/W)
must be reviewed to ensure that T
JM
is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
the
application’s
ambient
In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of P
DM
is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the R
θ
JA
for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction
temperature
or
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
power
dissipation.
Pulse
Displayed on the curve are R
θ
JA
values listed in the
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
P
DM
.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. R
θ
JA
is defined as the natural log of the area
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
(EQ. 1)
PDM
θ
JA
–
(
-----------------------------
)
=
(EQ. 2)
R
θ
JA
26.51
+
0.262
Area
(
)
-----------19.84
+
=
Figure 21. Thermal Resistance vs Mounting
Pad Area
20
40
60
80
1
10
0.1
R
θ
JA
= 26.51+ 19.84/(0.262+Area)
R
θ
J
(
o
C
AREA, TOP COPPER AREA (in
2
)
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