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| 型號(hào)： | FS6261-01 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Motherboard Clock Generator IC |
| 中文描述： | 主板時(shí)鐘發(fā)生器IC |
| 文件頁(yè)數(shù)： | 12/17頁(yè) |
| 文件大?。?/td> | 216K |
| 代理商： | FS6261-01 |
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XT
January 2000
1.31.00
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,62
Table 9: AC Timing Specifications, continued
Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature T
= 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and
are not currently production tested to any specific limits. MIN and MAX characterization data are
±
3
σ
from typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements.
133MHz
100MHz
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
UNITS
CPU_0:3 Clock Outputs (2.5V Type 1 Clock Buffer)
Duty Cycle *
d
t
Ratio of high pulse width to one
clock period, measured at 1.5V
45
49
55
45
49
55
%
Clock Skew *
t
skw
CPU to CPU @ 1.25V, C
L
=20pF
+60
+60
Jitter, Long Term (
σ
y
(
τ
)) *
t
j(LT)
On rising edges 500
μ
s apart at
1.25V relative to an ideal clock,
C
L
=20pF, all PLLs active
136
134
ps
Jitter, Period (peak-peak) *
t
j(
P)
From rising edge to rising edge at
1.25V, C
L
=20pF, all PLLs active
123
97
ps
t
r min
t
r max
t
f min
t
f max
t
DLH
t
DHL
Measured @ 0.4V – 2.0V; C
L
=10pF
1.1
1.4
1.0
1.1
0.9
1.4
0.9
1.2
Rise Time *
Measured @ 0.4V – 2.0V; C
L
=20pF
ns
Measured @ 2.0V – 0.4V; C
L
=10pF
Fall Time *
Measured @ 2.0V – 0.4V; C
L
=20pF
ns
Enable Delay *
via CPU_STOP#
1.0
8.0
1.0
8.0
ns
Disable Delay *
via CPU_STOP#
1.0
8.0
1.0
8.0
ns
REF_0:1 Clock Outputs (3.3V Type 3 Clock Buffer)
Duty Cycle *
d
t
Ratio of high pulse width to one
clock period, measured at 1.5V
45
50
55
45
50
55
%
Jitter, Long Term (
σ
y
(
τ
)) *
t
j(LT)
On rising edges 500
μ
s apart at 1.5V
relative to an ideal clock, C
L
=20pF,
all PLLs active
27
23
ps
Jitter, Period (peak-peak) *
t
j(
P)
From rising edge to rising edge at
1.5V, C
L
=20pF, all PLLs active
177
111
ps
t
r min
t
r max
t
f min
t
f max
Measured @ 0.4V – 2.4V; C
L
=10pF
0.9
1.4
1.0
1.6
0.9
1.4
1.0
1.6
Rise Time *
Measured @ 0.4V – 2.4V; C
L
=20pF
ns
Measured @ 2.4V – 0.4V; C
L
=10pF
Fall Time *
Measured @ 2.4V – 0.4V; C
L
=20pF
ns
CK48 Clock Output (3.3V Type 3 Clock Buffer)
Duty Cycle *
d
t
Ratio of high pulse width to one
clock period, measured at 1.5V
45
51
55
45
51
55
%
Jitter, Long Term (
σ
y
(
τ
)) *
t
j(LT)
On rising edges 500
μ
s apart at 1.5V
relative to an ideal clock, C
L
=20pF,
all PLLs active
244
246
ps
Jitter, Period (peak-peak) *
t
j(
P)
From rising edge to rising edge at
1.5V, C
L
=20pF, all PLLs active
143
202
ps
t
r min
t
r max
t
f min
t
f max
Measured @ 0.4V – 2.4V; C
L
=10pF
0.8
1.3
0.9
1.4
0.8
1.3
0.9
1.4
Rise Time *
Measured @ 0.4V – 2.4V; C
L
=20pF
ns
Measured @ 2.4V – 0.4V; C
L
=10pF
Fall Time *
Measured @ 2.4V – 0.4V; C
L
=20pF
ns
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