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參數(shù)資料
| 型號： | FS6261-01 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Motherboard Clock Generator IC |
| 中文描述： | 主板時鐘發(fā)生器IC |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 216K |
| 代理商： | FS6261-01 |
XT
January 2000
1.31.00
13
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,62
Table 9: AC Timing Specifications, continued
Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature T
= 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and
are not currently production tested to any specific limits. MIN and MAX characterization data are
±
3
σ
from typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements.
133MHz
100MHz
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
UNITS
PCI_1:7, PCI_F Clock Outputs (3.3V Type 5 Clock Buffer)
Duty Cycle *
d
t
Ratio of high pulse width to one
clock period, measured at 1.5V
45
47
55
45
50
55
%
PCI_F to PCI @ 1.5V, C
L
=30pF
+660
+60
+660
+60
Clock Skew *
t
skw
PCI to PCI @ 1.5V, C
L
=30pF
ps
Jitter, Long Term (
σ
y
(
τ
)) *
t
j(LT)
On rising edges 500
μ
s apart at 1.5V
relative to an ideal clock, C
L
=30pF,
all PLLs active
220
131
ps
Jitter, Period (peak-peak) *
t
j(
P)
From rising edge to rising edge at
1.5V, C
L
=30pF, all PLLs active
76
95
ps
t
r min
t
r max
t
f min
t
f max
t
DLH
t
DHL
Measured @ 0.4V – 2.4V; C
L
=10pF
1.2
1.8
1.3
1.6
1.3
1.8
1.2
1.5
Rise Time *
Measured @ 0.4V – 2.4V; C
L
=30pF
ns
Measured @ 2.4V – 0.4V; C
L
=10pF
Fall Time *
Measured @ 2.4V – 0.4V; C
L
=30pF
ns
Enable Delay *
Disable Delay *
via PCI_STOP#
via PCI_STOP#
1.0
1.0
8.0
8.0
1.0
1.0
8.0
8.0
ns
ns
CK66_0:3 Clock Outputs (3.3V Type 5 Clock Buffer)
Duty Cycle *
d
t
Ratio of high pulse width to one
clock period, measured at 1.5V
45
52
55
45
51
55
%
Clock Skew *
t
skw
CK66 to CK66 @ 1.5V, C
L
=30pF
120
120
ps
Jitter, Long Term (
σ
y
(
τ
)) *
t
j(LT)
On rising edges 500
μ
s apart at 1.5V
relative to an ideal clock, C
L
=30pF,
all PLLs on
137
123
ps
Jitter, Period (peak-peak) *
t
j(
P)
From rising edge to rising edge at
1.5V, C
L
=30pF, all PLLs active
75
79
ps
t
r min
t
r max
t
f min
t
f max
t
DLH
t
DHL
Measured @ 0.4V – 2.4V; C
L
=10pF
0.9
1.5
1.0
1.4
0.9
1.5
1.0
1.4
Rise Time *
Measured @ 0.4V – 2.4V; C
L
=30pF
ns
Measured @ 2.4V – 0.4V; C
L
=10pF
Fall Time *
Measured @ 2.4V – 0.4V; C
L
=30pF
ns
Enable Delay *
Disable Delay *
via CPU_STOP#
via CPU_STOP#
1.0
1.0
8.0
8.0
1.0
1.0
8.0
8.0
ns
ns
Figure 9: Clock Skew Diagrams
t
skw
t
skw
t
skw
3.3V
2.5V
1.25V
1.5V
2.5V
2.5V
1.25V
1.25V
3.3V
3.3V
1.5V
1.5V
2.5V to 3.3V Clock Offset
2.5V to 2.5V Clock Skew
3.3V to 3.3V Clock Skew
CPU
CK66
APIC
CPU
PCI
CK66
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