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參數(shù)資料
型號: FT2232D-REEL
廠商: FTDI, Future Technology Devices International Ltd
文件頁數(shù): 35/61頁
文件大?。?/td> 0K
描述: IC USB FS DUAL UART/FIFO 48-LQFP
產(chǎn)品培訓(xùn)模塊: USB Introduction
標(biāo)準(zhǔn)包裝: 1
系列: USBmadeEZ-FIFO,F(xiàn)T-X,X-Chip
特點(diǎn): USB 至 UART 和(或)FIFO、SPI、I2C、JTAG
通道數(shù): 2,DUART
FIFO's: 384 字節(jié)
規(guī)程: RS232,RS422,RS485
電源電壓: 4.35 V ~ 5.25 V
帶并行端口:
帶自動流量控制功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 634 (CN2011-ZH PDF)
配用: 768-1030-ND - MOD USB HS FT2232H EVAL
813-1009-ND - MODULE USB-TO-FPGA TOOL W/MANUAL
813-1001-ND - MODULE USB ADAPTR FOR FT2232D LP
813-1000-ND - MODULE USB ADAPTER FOR FT2232D
其它名稱: 768-1010-6
Copyright 2010 Future Technology Devices International Limited
40
Document No.: FT_000173
FT2232D DUAL USB TO SERIAL UART
/FIFO IC Datasheet
Version 2.05
Clearance No.: FTDI# 127
Figure 8.8 illustrates a typical interface between one of the channels of the FT2232D, configured in 245-
style FIFO interface mode, and a Microcontroller (MCU). Either channel A or B, or both can be configured
in this mode.
This examples uses two IO Ports of the MCU, one port (8 bits) to transfer data to one of the and the
other port (4 / 5 bits) to monitor the TXE# and RXF# status bits and generate the RD# and WR strobes
to the FT2232D as required. Optionally, SI / WU can be connected to another IO pin if either of the
functions of this pin are required. If the SI / WU function is not required, tie this pin to VCCIO. If the MCU
is handling power management functions, then PWREN# should also be connected to an IO pin of the
MCU.
The 8 data bits on IO Port 1 can be shared with other peripherals when the MCU is not accessing the
FT2232D
8.4 Enhanced Asynchronous and Synchronous Bit-Bang Modes - Signal
Description and Interface Configuration
Bit-bang mode is a special FT2232D device mode that changes the 8 IO lines on either (or both) channels
into an 8 bit bi-directional data bus. The are two types of Bit-bang mode for the FT2232D - Enhanced
Asynchronous Bit-Bang Mode, which is virtually the same as FTDI BM chip-style Bit-Bang mode, with the
addition of Read and Write strobes; and Synchronous Bit-Bang mode, where data is only read from the
device when the device is written to. Bit-Bang mode is enabled by driver command. When either Channel
A or Channel B (or both) have Enhanced Asynchronous Bit-Bang mode, or Synchronous Bit-Bang mode
enabled the IO signal lines are configured as follows :-
Pin#
Signal
Type
Description
Channel A
Channel B
24
40
D0
I/O
Bit-Bang Data Bus Bit 0
23
39
D1
I/O
Bit-Bang Data Bus Bit 1
22
38
D2
I/O
Bit-Bang Data Bus Bit 2
21
37
D3
I/O
Bit-Bang Data Bus Bit 3
20
36
D4
I/O
Bit-Bang Data Bus Bit 4
19
35
D5
I/O
Bit-Bang Data Bus Bit 5
17
33
D6
I/O
Bit-Bang Data Bus Bit 6
16
32
D7
I/O
Bit-Bang Data Bus Bit 7
Table 8.6 Bit-Bang Data Bus Group **Note 24
**Note 24: In Input Mode, these pins are pulled to VCCIO via internal 200K resistors. These can be
programmed to gently pull low during USB suspend (PWREN# = “1” ) by setting this option in the
EEPROM.
Pin#
Signal
Type
Description
Channel A
Channel B
15
30
WR#
OUTPUT
**Note 25
13
29
RD#
OUTPUT
**Note 25
12
28
WR#
INPUT
**Note 26
11
27
RD#
INPUT
**Note 26
10
26
SI/WU
INPUT
The Send Immediate / WakeUp signal combines two
functions on a single pin. If USB is in suspend mode
(PWREN# = 1) and remote wakeup is enabled in the
EEPROM , strobing this pin low will cause the device to
request a resume on the USB Bus. Normally, this can be
used to wake up the Host PC.
During normal operation (PWREN# = 0), if this pin is
strobed low any data in the device TX buffer will be sent
out over USB on the next Bulk-IN request from the
drivers regardless of the pending packet size. This can
be used to optimise USB transfer speed for some
applications. Tie this pin to VCCIO if not used
Table 8.7 Bit-Bang Control Interface Group
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