/FIFO IC <" />
參數(shù)資料
型號: FT2232D-REEL
廠商: FTDI, Future Technology Devices International Ltd
文件頁數(shù): 42/61頁
文件大?。?/td> 0K
描述: IC USB FS DUAL UART/FIFO 48-LQFP
產(chǎn)品培訓(xùn)模塊: USB Introduction
標(biāo)準(zhǔn)包裝: 1
系列: USBmadeEZ-FIFO,F(xiàn)T-X,X-Chip
特點(diǎn): USB 至 UART 和(或)FIFO、SPI、I2C、JTAG
通道數(shù): 2,DUART
FIFO's: 384 字節(jié)
規(guī)程: RS232,RS422,RS485
電源電壓: 4.35 V ~ 5.25 V
帶并行端口:
帶自動流量控制功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 634 (CN2011-ZH PDF)
配用: 768-1030-ND - MOD USB HS FT2232H EVAL
813-1009-ND - MODULE USB-TO-FPGA TOOL W/MANUAL
813-1001-ND - MODULE USB ADAPTR FOR FT2232D LP
813-1000-ND - MODULE USB ADAPTER FOR FT2232D
其它名稱: 768-1010-6
Copyright 2010 Future Technology Devices International Limited
47
Document No.: FT_000173
FT2232D DUAL USB TO SERIAL UART
/FIFO IC Datasheet
Version 2.05
Clearance No.: FTDI# 127
Time
Description
Min
Typical
Value
Max
Unit
tperiod
Clock Period
41.6
83.3
125.0
ns
thigh
Clock signal high
time
20.8
41.6
62.5
ns
tlow
Clock signal low
time
20.8
41.6
62.5
ns
Table 8.13 MCU Host Bus Emulation Mode Signal Timing - Clock (OSC) Signal
Figure 8.13 MCU Host Bus Emulation Example - USB <=> CAN Bus Interface
Figure 8.13 shows an example where the FT2232D is used to interface a Philips SJA1000 CAN Bus
Controller to a PC over USB. In this example IORDY is not used and so is pulled up to Vcc. I/O1 is used to
monitor the Interrupt output (INT) of the SJA1000. The MODE pin on the SJA1000 is pulled high to select
Intel mode. See the semiconductors section of the Philips website (www.philips.com) for more details
on the SJA1000 and suitable CAN Bus transceiver devices.
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